897 	i915_reg_t ctl, cfgcr1, cfgcr2;  member
910 		.cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
916 		.cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
922 		.cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
952 	I915_WRITE(regs[id].cfgcr1, pll->state.hw_state.cfgcr1);  in skl_ddi_pll_enable()
954 	POSTING_READ(regs[id].cfgcr1);  in skl_ddi_pll_enable()
1015 		hw_state->cfgcr1 = I915_READ(regs[id].cfgcr1);  in skl_ddi_pll_get_hw_state()
1306 	uint32_t ctrl1, cfgcr1, cfgcr2;  in skl_ddi_hdmi_pll_dividers()  local
1320 	cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |  in skl_ddi_hdmi_pll_dividers()
1334 	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;  in skl_ddi_hdmi_pll_dividers()
1426 		      hw_state->cfgcr1,  in skl_dump_hw_state()
1997 		val = pll->state.hw_state.cfgcr1;  in cnl_ddi_pll_enable()
2118 		hw_state->cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(id));  in cnl_ddi_pll_get_hw_state()
2274 	uint32_t cfgcr0, cfgcr1;  in cnl_ddi_hdmi_pll_dividers()  local
2285 	cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(wrpll_params.qdiv_ratio) |  in cnl_ddi_hdmi_pll_dividers()
2295 	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;  in cnl_ddi_hdmi_pll_dividers()
2390 		      hw_state->cfgcr1);  in cnl_dump_hw_state()
2502 	uint32_t cfgcr0, cfgcr1;  in icl_calc_dpll_state()  local
2517 	cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) |  in icl_calc_dpll_state()
2524 	pll_state->cfgcr1 = cfgcr1;  in icl_calc_dpll_state()
2531 	uint32_t cfgcr0, cfgcr1;  in icl_calc_dp_combo_pll_link()  local
2538 	cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));  in icl_calc_dp_combo_pll_link()
2543 	pdiv = (cfgcr1 & DPLL_CFGCR1_PDIV_MASK) >> DPLL_CFGCR1_PDIV_SHIFT;  in icl_calc_dp_combo_pll_link()
2544 	kdiv = (cfgcr1 & DPLL_CFGCR1_KDIV_MASK) >> DPLL_CFGCR1_KDIV_SHIFT;  in icl_calc_dp_combo_pll_link()
2545 	qdiv_mode = (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) >>  in icl_calc_dp_combo_pll_link()
2547 	qdiv_ratio = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>  in icl_calc_dp_combo_pll_link()
2943 		hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));  in icl_pll_get_hw_state()
3004 	I915_WRITE(ICL_DPLL_CFGCR1(id), hw_state->cfgcr1);  in icl_dpll_write()
3157 		      hw_state->cfgcr0, hw_state->cfgcr1,  in icl_dump_hw_state()