Searched refs:cfgcr0 (Results 1 – 5 of 5) sorted by relevance
1988 val = pll->state.hw_state.cfgcr0; in cnl_ddi_pll_enable()1996 if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) { in cnl_ddi_pll_enable()2114 hw_state->cfgcr0 = val; in cnl_ddi_pll_get_hw_state()2274 uint32_t cfgcr0, cfgcr1; in cnl_ddi_hdmi_pll_dividers() local2277 cfgcr0 = DPLL_CFGCR0_HDMI_MODE; in cnl_ddi_hdmi_pll_dividers()2282 cfgcr0 |= DPLL_CFGCR0_DCO_FRACTION(wrpll_params.dco_fraction) | in cnl_ddi_hdmi_pll_dividers()2294 crtc_state->dpll_hw_state.cfgcr0 = cfgcr0; in cnl_ddi_hdmi_pll_dividers()2303 uint32_t cfgcr0; in cnl_ddi_dp_set_dpll_hw_state() local2305 cfgcr0 = DPLL_CFGCR0_SSC_ENABLE; in cnl_ddi_dp_set_dpll_hw_state()2309 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_810; in cnl_ddi_dp_set_dpll_hw_state()[all …]
162 uint32_t cfgcr0; member
1369 uint32_t cfgcr0, cfgcr1; in cnl_calc_wrpll_link() local1373 cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id)); in cnl_calc_wrpll_link()1376 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id)); in cnl_calc_wrpll_link()1419 dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock; in cnl_calc_wrpll_link()1421 dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> in cnl_calc_wrpll_link()1483 uint32_t cfgcr0; in cnl_ddi_clock_get() local1488 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id)); in cnl_ddi_clock_get()1490 if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) { in cnl_ddi_clock_get()1493 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK; in cnl_ddi_clock_get()
3308 seq_printf(m, " cfgcr0: 0x%08x\n", pll->state.hw_state.cfgcr0); in i915_shared_dplls_info()
11556 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); in intel_pipe_config_compare()
