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Searched refs:bit_idx (Results 1 – 25 of 82) sorted by relevance

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/Linux-v4.19/drivers/clk/
Dclk-gate.c57 reg = BIT(gate->bit_idx + 16); in clk_gate_endisable()
59 reg |= BIT(gate->bit_idx); in clk_gate_endisable()
64 reg |= BIT(gate->bit_idx); in clk_gate_endisable()
66 reg &= ~BIT(gate->bit_idx); in clk_gate_endisable()
98 reg ^= BIT(gate->bit_idx); in clk_gate_is_enabled()
100 reg &= BIT(gate->bit_idx); in clk_gate_is_enabled()
126 void __iomem *reg, u8 bit_idx, in clk_hw_register_gate() argument
135 if (bit_idx > 15) { in clk_hw_register_gate()
154 gate->bit_idx = bit_idx; in clk_hw_register_gate()
172 void __iomem *reg, u8 bit_idx, in clk_register_gate() argument
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Dclk-stm32f4.c60 u8 bit_idx; member
342 u8 bit_idx; member
352 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) in clk_apb_mul_recalc_rate()
364 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) in clk_apb_mul_round_rate()
396 unsigned long flags, u8 bit_idx) in clk_register_apb_mul() argument
406 am->bit_idx = bit_idx; in clk_register_apb_mul()
471 u8 bit_idx; member
743 pll->gate.bit_idx = vco->bit_idx; in stm32f4_rcc_register_pll()
749 pll->status = (readl(base + STM32F4_RCC_CR) >> vco->bit_idx) & 0x1; in stm32f4_rcc_register_pll()
891 void __iomem *reg, u8 bit_idx, u8 bit_rdy_idx, in clk_register_rgate() argument
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Dclk-stm32h7.c217 void __iomem *reg, u8 bit_idx, u8 bit_rdy, in clk_register_ready_gate() argument
238 rgate->gate.bit_idx = bit_idx; in clk_register_ready_gate()
253 u8 bit_idx; member
332 static struct clk_gate *_get_cgate(void __iomem *reg, u8 bit_idx, u32 flags, in _get_cgate() argument
342 gate->bit_idx = bit_idx; in _get_cgate()
402 cfg->gate->bit_idx, in get_cfg_composite_div()
593 u8 bit_idx; member
603 .bit_idx = _bit_idx,\
622 u8 bit_idx; member
637 .bit_idx = 24,
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Dclk-asm9260.c86 u8 bit_idx; member
313 base + gd->reg, gd->bit_idx, 0, &asm9260_clk_lock); in asm9260_acc_init()
332 gd->bit_idx, 0, &asm9260_clk_lock); in asm9260_acc_init()
/Linux-v4.19/drivers/clk/imx/
Dclk-gate2.c33 u8 bit_idx; member
54 reg &= ~(3 << gate->bit_idx); in clk_gate2_enable()
55 reg |= gate->cgr_val << gate->bit_idx; in clk_gate2_enable()
80 reg &= ~(3 << gate->bit_idx); in clk_gate2_disable()
87 static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx) in clk_gate2_reg_is_enabled() argument
91 if (((val >> bit_idx) & 1) == 1) in clk_gate2_reg_is_enabled()
101 return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx); in clk_gate2_is_enabled()
114 reg &= ~(3 << gate->bit_idx); in clk_gate2_disable_unused()
130 void __iomem *reg, u8 bit_idx, u8 cgr_val, in clk_register_gate2() argument
144 gate->bit_idx = bit_idx; in clk_register_gate2()
/Linux-v4.19/drivers/xen/events/
Devents_2l.c168 int word_idx, bit_idx; in evtchn_2l_handle_events() local
178 bit_idx = evtchn % BITS_PER_LONG; in evtchn_2l_handle_events()
179 if (active_evtchns(cpu, s, word_idx) & (1ULL << bit_idx)) in evtchn_2l_handle_events()
205 bit_idx = 0; in evtchn_2l_handle_events()
211 bit_idx = 0; /* usually scan entire word from start */ in evtchn_2l_handle_events()
226 bit_idx = start_bit_idx; in evtchn_2l_handle_events()
233 bits = MASK_LSBS(pending_bits, bit_idx); in evtchn_2l_handle_events()
239 bit_idx = EVTCHN_FIRST_BIT(bits); in evtchn_2l_handle_events()
242 port = (word_idx * BITS_PER_EVTCHN_WORD) + bit_idx; in evtchn_2l_handle_events()
248 bit_idx = (bit_idx + 1) % BITS_PER_EVTCHN_WORD; in evtchn_2l_handle_events()
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/Linux-v4.19/drivers/clk/hisilicon/
Dclkgate-separated.c41 u8 bit_idx; /* bits in enable/disable register */ member
55 reg = BIT(sclk->bit_idx); in clkgate_separated_enable()
72 reg = BIT(sclk->bit_idx); in clkgate_separated_disable()
86 reg &= BIT(sclk->bit_idx); in clkgate_separated_is_enabled()
100 void __iomem *reg, u8 bit_idx, in hisi_register_clkgate_sep() argument
118 sclk->bit_idx = bit_idx; in hisi_register_clkgate_sep()
/Linux-v4.19/drivers/clk/meson/
Dmeson8b.c228 .bit_idx = 27,
259 .bit_idx = 28,
283 .bit_idx = 29,
307 .bit_idx = 30,
331 .bit_idx = 31,
390 .bit_idx = 14,
431 .bit_idx = 14,
472 .bit_idx = 14,
522 .bit_idx = 7,
673 .bit_idx = 8,
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Daxg.c315 .bit_idx = 27,
339 .bit_idx = 28,
363 .bit_idx = 29,
387 .bit_idx = 30,
411 .bit_idx = 31,
476 .bit_idx = 14,
523 .bit_idx = 14,
570 .bit_idx = 14,
617 .bit_idx = 0,
733 .bit_idx = 4,
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Dgxbb.c493 .bit_idx = 27,
518 .bit_idx = 28,
542 .bit_idx = 29,
566 .bit_idx = 30,
590 .bit_idx = 31,
649 .bit_idx = 14,
690 .bit_idx = 14,
731 .bit_idx = 14,
786 .bit_idx = 7,
829 .bit_idx = 8,
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Dclk-regmap.c17 return regmap_update_bits(clk->map, gate->offset, BIT(gate->bit_idx), in clk_regmap_gate_endisable()
18 set ? BIT(gate->bit_idx) : 0); in clk_regmap_gate_endisable()
39 val ^= BIT(gate->bit_idx); in clk_regmap_gate_is_enabled()
41 val &= BIT(gate->bit_idx); in clk_regmap_gate_is_enabled()
Daxg-aoclk.c23 .bit_idx = (_bit), \
88 .bit_idx = 8,
Dclk-regmap.h43 u8 bit_idx; member
/Linux-v4.19/drivers/clk/actions/
Dowl-gate.c27 reg |= BIT(gate_hw->bit_idx); in owl_gate_set()
29 reg &= ~BIT(gate_hw->bit_idx); in owl_gate_set()
60 reg ^= BIT(gate_hw->bit_idx); in owl_gate_clk_is_enabled()
62 return !!(reg & BIT(gate_hw->bit_idx)); in owl_gate_clk_is_enabled()
Dowl-gate.h18 u8 bit_idx; member
30 .bit_idx = _bit_idx, \
Dowl-pll.h25 u8 bit_idx; member
43 .bit_idx = _bit_idx, \
Dowl-pll.c119 return !!(reg & BIT(pll_hw->bit_idx)); in owl_pll_is_enabled()
130 reg |= BIT(pll_hw->bit_idx); in owl_pll_set()
132 reg &= ~BIT(pll_hw->bit_idx); in owl_pll_set()
/Linux-v4.19/drivers/clk/mvebu/
Dcp110-system-controller.c118 u8 bit_idx; member
128 BIT(gate->bit_idx), BIT(gate->bit_idx)); in cp110_gate_enable()
138 BIT(gate->bit_idx), 0); in cp110_gate_disable()
148 return val & BIT(gate->bit_idx); in cp110_gate_is_enabled()
159 struct regmap *regmap, u8 bit_idx) in cp110_register_gate() argument
178 gate->bit_idx = bit_idx; in cp110_register_gate()
Dcommon.h43 int bit_idx; member
/Linux-v4.19/drivers/clk/st/
Dclk-flexgen.c163 reg &= ~BIT(config->bit_idx); in flexgen_set_rate()
232 fgxbar->pgate.bit_idx = xbar_shift + 6; in clk_register_flexgen()
242 fgxbar->fgate.bit_idx = 6; in clk_register_flexgen()
252 fgxbar->sync.bit_idx = 7; in clk_register_flexgen()
/Linux-v4.19/drivers/clk/ti/
Dinterface.c37 struct clk_omap_reg *reg, u8 bit_idx, in _register_interface() argument
51 clk_hw->enable_bit = bit_idx; in _register_interface()
Dgate.c95 struct clk_omap_reg *reg, u8 bit_idx, in _register_gate() argument
113 clk_hw->enable_bit = bit_idx; in _register_gate()
/Linux-v4.19/drivers/clk/berlin/
Dcommon.h14 u8 bit_idx; member
/Linux-v4.19/drivers/clk/sunxi/
Dclk-a10-hosc.c49 gate->bit_idx = SUNXI_OSC24M_GATE; in sun4i_osc_clk_setup()
Dclk-a20-gmac.c91 gate->bit_idx = SUN7I_A20_GMAC_GPIT; in sun7i_a20_gmac_clk_setup()

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