Searched refs:allowed_mclk_table (Results 1 – 2 of 2) sorted by relevance
3444 struct radeon_clock_voltage_dependency_table *allowed_mclk_table = in ci_setup_default_dpm_tables() local3454 if (allowed_mclk_table == NULL) in ci_setup_default_dpm_tables()3456 if (allowed_mclk_table->count < 1) in ci_setup_default_dpm_tables()3491 for (i = 0; i < allowed_mclk_table->count; i++) { in ci_setup_default_dpm_tables()3494 allowed_mclk_table->entries[i].clk)) { in ci_setup_default_dpm_tables()3496 allowed_mclk_table->entries[i].clk; in ci_setup_default_dpm_tables()3512 allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; in ci_setup_default_dpm_tables()3513 if (allowed_mclk_table) { in ci_setup_default_dpm_tables()3514 for (i = 0; i < allowed_mclk_table->count; i++) { in ci_setup_default_dpm_tables()3516 allowed_mclk_table->entries[i].v; in ci_setup_default_dpm_tables()[all …]
3587 struct amdgpu_clock_voltage_dependency_table *allowed_mclk_table = in ci_setup_default_dpm_tables() local3597 if (allowed_mclk_table == NULL) in ci_setup_default_dpm_tables()3599 if (allowed_mclk_table->count < 1) in ci_setup_default_dpm_tables()3634 for (i = 0; i < allowed_mclk_table->count; i++) { in ci_setup_default_dpm_tables()3637 allowed_mclk_table->entries[i].clk)) { in ci_setup_default_dpm_tables()3639 allowed_mclk_table->entries[i].clk; in ci_setup_default_dpm_tables()3655 allowed_mclk_table = &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk; in ci_setup_default_dpm_tables()3656 if (allowed_mclk_table) { in ci_setup_default_dpm_tables()3657 for (i = 0; i < allowed_mclk_table->count; i++) { in ci_setup_default_dpm_tables()3659 allowed_mclk_table->entries[i].v; in ci_setup_default_dpm_tables()[all …]
