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Searched refs:WREG32_SMC (Results 1 – 23 of 23) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/radeon/
Dtrinity_smc.c67 WREG32_SMC(SMU_SCRATCH0, 1); in trinity_dpm_config()
69 WREG32_SMC(SMU_SCRATCH0, 0); in trinity_dpm_config()
76 WREG32_SMC(SMU_SCRATCH0, n); in trinity_dpm_force_state()
83 WREG32_SMC(SMU_SCRATCH0, n); in trinity_dpm_n_levels_disabled()
Dtrinity_dpm.c382 WREG32_SMC(GFX_POWER_GATING_CNTL, value); in trinity_gfx_powergating_initialize()
506 WREG32_SMC(SMU_SCRATCH_A, (RREG32_SMC(SMU_SCRATCH_A) | 0x01)); in trinity_gfx_powergating_enable()
524 WREG32_SMC(PM_I_CNTL_1, value); in trinity_gfx_dynamic_mgpg_enable()
529 WREG32_SMC(SMU_S_PG_CNTL, value); in trinity_gfx_dynamic_mgpg_enable()
533 WREG32_SMC(SMU_S_PG_CNTL, value); in trinity_gfx_dynamic_mgpg_enable()
537 WREG32_SMC(PM_I_CNTL_1, value); in trinity_gfx_dynamic_mgpg_enable()
598 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); in trinity_set_divider_value()
608 WREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix, value); in trinity_set_divider_value()
620 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_ds_dividers()
632 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_ss_dividers()
[all …]
Dci_smc.c119 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in ci_start_smc()
127 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in ci_reset_smc()
143 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in ci_stop_smc_clock()
152 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in ci_start_smc_clock()
Dsi_smc.c119 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in si_start_smc()
133 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in si_reset_smc()
149 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in si_stop_smc_clock()
158 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in si_start_smc_clock()
Dci_dpm.c598 WREG32_SMC(config_regs->offset, data); in ci_program_pt_config_registers()
888 WREG32_SMC(CG_THERMAL_INT, tmp); in ci_thermal_set_temperature_range()
895 WREG32_SMC(CG_THERMAL_CTRL, tmp); in ci_thermal_set_temperature_range()
912 WREG32_SMC(CG_THERMAL_INT, thermal_int); in ci_thermal_enable_alert()
921 WREG32_SMC(CG_THERMAL_INT, thermal_int); in ci_thermal_enable_alert()
948 WREG32_SMC(CG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_static_mode()
952 WREG32_SMC(CG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_static_mode()
1126 WREG32_SMC(CG_FDO_CTRL0, tmp); in ci_fan_ctrl_set_fan_speed_percent()
1203 WREG32_SMC(CG_TACH_CTRL, tmp);
1219 WREG32_SMC(CG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_default_mode()
[all …]
Dkv_dpm.c275 WREG32_SMC(local_cac_reg->cntl, data);
315 WREG32_SMC(config_regs->offset, data); in kv_program_pt_config_registers()
406 WREG32_SMC(LCAC_SX0_OVR_SEL, 0);
407 WREG32_SMC(LCAC_SX0_OVR_VAL, 0);
410 WREG32_SMC(LCAC_MC0_OVR_SEL, 0);
411 WREG32_SMC(LCAC_MC0_OVR_VAL, 0);
414 WREG32_SMC(LCAC_MC1_OVR_SEL, 0);
415 WREG32_SMC(LCAC_MC1_OVR_VAL, 0);
418 WREG32_SMC(LCAC_MC2_OVR_SEL, 0);
419 WREG32_SMC(LCAC_MC2_OVR_VAL, 0);
[all …]
Dcik.c9439 WREG32_SMC(cntl_reg, tmp); in cik_set_uvd_clock()
9486 WREG32_SMC(CG_ECLK_CNTL, tmp); in cik_set_vce_clocks()
9761 WREG32_SMC(THM_CLK_CNTL, data); in cik_program_aspm()
9767 WREG32_SMC(MISC_CLK_CTRL, data); in cik_program_aspm()
9772 WREG32_SMC(CG_CLKPIN_CNTL, data); in cik_program_aspm()
9777 WREG32_SMC(CG_CLKPIN_CNTL_2, data); in cik_program_aspm()
9783 WREG32_SMC(MPLL_BYPASSCLK_SEL, data); in cik_program_aspm()
Dsi.c5462 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0); in si_enable_uvd_mgcg()
5463 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0); in si_enable_uvd_mgcg()
5474 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0xffffffff); in si_enable_uvd_mgcg()
5475 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0xffffffff); in si_enable_uvd_mgcg()
Dradeon.h2537 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) macro
2571 WREG32_SMC(reg, tmp_); \
Dsi_dpm.c2763 WREG32_SMC(offset, data); in si_program_cac_config_registers()
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dci_smc.c122 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, tmp); in amdgpu_ci_start_smc()
130 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, tmp); in amdgpu_ci_reset_smc()
146 WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, tmp); in amdgpu_ci_stop_smc_clock()
155 WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, tmp); in amdgpu_ci_start_smc_clock()
Dsi_smc.c117 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in amdgpu_si_start_smc()
131 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in amdgpu_si_reset_smc()
150 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in amdgpu_si_smc_clock()
Dci_dpm.c723 WREG32_SMC(config_regs->offset, data); in ci_program_pt_config_registers()
1026 WREG32_SMC(ixCG_THERMAL_INT, tmp); in ci_thermal_set_temperature_range()
1033 WREG32_SMC(ixCG_THERMAL_CTRL, tmp); in ci_thermal_set_temperature_range()
1050 WREG32_SMC(ixCG_THERMAL_INT, thermal_int); in ci_thermal_enable_alert()
1059 WREG32_SMC(ixCG_THERMAL_INT, thermal_int); in ci_thermal_enable_alert()
1087 WREG32_SMC(ixCG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_static_mode()
1091 WREG32_SMC(ixCG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_static_mode()
1274 WREG32_SMC(ixCG_FDO_CTRL0, tmp); in ci_dpm_set_fan_speed_percent()
1358 WREG32_SMC(CG_TACH_CTRL, tmp);
1374 WREG32_SMC(ixCG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_default_mode()
[all …]
Dkv_dpm.c404 WREG32_SMC(local_cac_reg->cntl, data);
444 WREG32_SMC(config_regs->offset, data); in kv_program_pt_config_registers()
535 WREG32_SMC(ixLCAC_SX0_OVR_SEL, 0);
536 WREG32_SMC(ixLCAC_SX0_OVR_VAL, 0);
539 WREG32_SMC(ixLCAC_MC0_OVR_SEL, 0);
540 WREG32_SMC(ixLCAC_MC0_OVR_VAL, 0);
543 WREG32_SMC(ixLCAC_MC1_OVR_SEL, 0);
544 WREG32_SMC(ixLCAC_MC1_OVR_VAL, 0);
547 WREG32_SMC(ixLCAC_MC2_OVR_SEL, 0);
548 WREG32_SMC(ixLCAC_MC2_OVR_VAL, 0);
[all …]
Dcik.c920 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); in cik_read_disabled_bios()
931 WREG32_SMC(ixROM_CNTL, rom_cntl); in cik_read_disabled_bios()
1315 WREG32_SMC(cntl_reg, tmp); in cik_set_uvd_clock()
1364 WREG32_SMC(ixCG_ECLK_CNTL, tmp); in cik_set_vce_clocks()
1650 WREG32_SMC(ixTHM_CLK_CNTL, data); in cik_program_aspm()
1658 WREG32_SMC(ixMISC_CLK_CTRL, data); in cik_program_aspm()
1663 WREG32_SMC(ixCG_CLKPIN_CNTL, data); in cik_program_aspm()
1668 WREG32_SMC(ixCG_CLKPIN_CNTL_2, data); in cik_program_aspm()
1674 WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data); in cik_program_aspm()
Dvi.c404 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); in vi_read_disabled_bios()
415 WREG32_SMC(ixROM_CNTL, rom_cntl); in vi_read_disabled_bios()
739 WREG32_SMC(cntl_reg, tmp); in vi_set_uvd_clock()
829 WREG32_SMC(reg_ctrl, tmp); in vi_set_vce_clocks()
1354 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data); in vi_update_rom_medium_grain_clock_gating()
Damdgpu_cgs.c95 return WREG32_SMC(index, value); in amdgpu_cgs_write_ind_register()
Damdgpu_debugfs.c443 WREG32_SMC(*pos, value); in amdgpu_debugfs_regs_smc_write()
Dvce_v4_0.c877 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
Dsi_dpm.c2863 WREG32_SMC(offset, data); in si_program_cac_config_registers()
7514 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state()
7519 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state()
7531 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state()
7536 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state()
Damdgpu.h1610 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) macro
Duvd_v7_0.c1686 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
Dgfx_v8_0.c790 WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C); in gfx_v8_0_init_golden_registers()