Searched refs:WP (Results 1 – 25 of 40) sorted by relevance
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24 - wp-inverted: when present, polarity on the WP line is inverted. See the note25 below for the case, when a GPIO is used for the WP line26 - disable-wp: When set no physical WP line is present. This property should29 logic it is sufficient to not specify wp-gpios property in the absence of a WP66 *NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line73 CD and WP lines can be implemented on the hardware in one of two ways: as GPIOs,77 in the latter case. We choose to use the XOR logic for GPIO CD and WP lines.
21 /* No CD or WP GPIOs */
39 MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
284 /* WP */299 /* WP */
95 AT91_PIOC 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* WP pin */
77 /* No CD or WP GPIOs */
49 /* No WP GPIO */
192 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */235 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
87 * No CD or WP GPIOs: SDIO interface used for
85 /* No CD or WP GPIOs */
104 /* No WP GPIO */
106 /* No CD or WP GPIOs */
549 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* SD2 WP */562 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* SD3 WP */
90 AT91_PIOE 19 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PE19 gpio WP pin pull up */
577 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */620 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
131 /* No CD or WP GPIOs */
97 /* No CD or WP GPIOs */
73 /* No CD or WP GPIOs */
170 MX27_PAD_SSI3_FS__GPIO3_28 0x0 /* WP */
153 AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD29 gpio WP pin pull up */
57 * 1.0 MMC WP
227 MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */
41 #define WP (0x01 << 24) macro227 val |= WP; in nuc900_nand_enable()
52 (WP) control bit. It is always available on >=54 earlier versions of this core that include WP
175 case PAT_WP: cache = CM(WP); cache_mode = "WP "; break; in pat_get_cache_mode()363 PAT(4, WB) | PAT(5, WP) | PAT(6, UC_MINUS) | PAT(7, WT); in pat_init()
