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Searched refs:VC4_SET_FIELD (Results 1 – 12 of 12) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/vc4/
Dvc4_dsi.c932 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | in vc4_dsi_encoder_enable()
933 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ)); in vc4_dsi_encoder_enable()
944 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE1) | in vc4_dsi_encoder_enable()
945 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE0) | in vc4_dsi_encoder_enable()
946 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_CLANE)); in vc4_dsi_encoder_enable()
948 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | in vc4_dsi_encoder_enable()
949 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ) | in vc4_dsi_encoder_enable()
950 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_CLANE) | in vc4_dsi_encoder_enable()
951 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE0) | in vc4_dsi_encoder_enable()
952 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE1) | in vc4_dsi_encoder_enable()
[all …]
Dvc4_plane.c379 VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) | in vc4_write_tpz()
380 VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE)); in vc4_write_tpz()
382 VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP)); in vc4_write_tpz()
391 VC4_SET_FIELD(scale, SCALER_PPF_SCALE) | in vc4_write_ppf()
392 VC4_SET_FIELD(0, SCALER_PPF_IPHASE)); in vc4_write_ppf()
519 pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH); in vc4_plane_mode_set()
533 pitch0 = (VC4_SET_FIELD(0, SCALER_PITCH0_TILE_Y_OFFSET) | in vc4_plane_mode_set()
534 VC4_SET_FIELD(0, SCALER_PITCH0_TILE_WIDTH_L) | in vc4_plane_mode_set()
535 VC4_SET_FIELD(tiles_w, SCALER_PITCH0_TILE_WIDTH_R)); in vc4_plane_mode_set()
578 pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT); in vc4_plane_mode_set()
[all …]
Dvc4_kms.c112 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]), in vc4_ctm_commit()
114 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]), in vc4_ctm_commit()
116 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]), in vc4_ctm_commit()
119 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]), in vc4_ctm_commit()
121 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]), in vc4_ctm_commit()
123 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]), in vc4_ctm_commit()
126 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]), in vc4_ctm_commit()
128 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]), in vc4_ctm_commit()
130 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[8]), in vc4_ctm_commit()
135 VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO)); in vc4_ctm_commit()
Dvc4_hdmi.c504 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, in vc4_hdmi_encoder_enable()
506 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, in vc4_hdmi_encoder_enable()
508 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); in vc4_hdmi_encoder_enable()
509 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | in vc4_hdmi_encoder_enable()
510 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, in vc4_hdmi_encoder_enable()
512 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | in vc4_hdmi_encoder_enable()
513 VC4_SET_FIELD(mode->crtc_vtotal - in vc4_hdmi_encoder_enable()
568 VC4_SET_FIELD(mode->hdisplay * pixel_rep, in vc4_hdmi_encoder_enable()
572 VC4_SET_FIELD((mode->htotal - in vc4_hdmi_encoder_enable()
575 VC4_SET_FIELD((mode->hsync_end - in vc4_hdmi_encoder_enable()
[all …]
Dvc4_crtc.c348 VC4_SET_FIELD((mode->htotal - in vc4_crtc_config_pv()
351 VC4_SET_FIELD((mode->hsync_end - in vc4_crtc_config_pv()
355 VC4_SET_FIELD((mode->hsync_start - in vc4_crtc_config_pv()
358 VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE)); in vc4_crtc_config_pv()
361 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, in vc4_crtc_config_pv()
363 VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, in vc4_crtc_config_pv()
366 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, in vc4_crtc_config_pv()
368 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); in vc4_crtc_config_pv()
372 VC4_SET_FIELD(mode->crtc_vtotal - in vc4_crtc_config_pv()
375 VC4_SET_FIELD(mode->crtc_vsync_end - in vc4_crtc_config_pv()
[all …]
Dvc4_dpi.c194 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, in vc4_dpi_encoder_enable()
198 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, in vc4_dpi_encoder_enable()
200 dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER); in vc4_dpi_encoder_enable()
203 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_2, in vc4_dpi_encoder_enable()
207 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1, in vc4_dpi_encoder_enable()
211 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_3, in vc4_dpi_encoder_enable()
220 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, DPI_FORMAT); in vc4_dpi_encoder_enable()
Dvc4_txp.c315 VC4_SET_FIELD(0xf, TXP_BYTE_ENABLE) | in vc4_txp_connector_atomic_commit()
316 VC4_SET_FIELD(txp_fmts[i], TXP_FORMAT); in vc4_txp_connector_atomic_commit()
325 VC4_SET_FIELD(mode->hdisplay, TXP_WIDTH) | in vc4_txp_connector_atomic_commit()
326 VC4_SET_FIELD(mode->vdisplay, TXP_HEIGHT)); in vc4_txp_connector_atomic_commit()
Dvc4_gem.c434 VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) | in vc4_flush_caches()
435 VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC) | in vc4_flush_caches()
436 VC4_SET_FIELD(0xf, V3D_SLCACTL_UCC) | in vc4_flush_caches()
437 VC4_SET_FIELD(0xf, V3D_SLCACTL_ICC)); in vc4_flush_caches()
449 VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) | in vc4_flush_texture_caches()
450 VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC)); in vc4_flush_texture_caches()
Dvc4_hvs.c227 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX); in vc4_hvs_bind()
Dvc4_validate.c409 VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32, in validate_tile_binning_config()
411 VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_128, in validate_tile_binning_config()
Dvc4_render_cl.c84 VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_NONE, in vc4_store_before_load()
Dvc4_regs.h16 #define VC4_SET_FIELD(value, field) \ macro