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Searched refs:UvdLevel (Results 1 – 17 of 17) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/powerplay/smumgr/
Dvegam_smumgr.c1333 table->UvdLevel[count].MinVoltage = 0; in vegam_populate_smc_uvd_level()
1334 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk; in vegam_populate_smc_uvd_level()
1335 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk; in vegam_populate_smc_uvd_level()
1336 table->UvdLevel[count].MinVoltage |= in vegam_populate_smc_uvd_level()
1347 table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT; in vegam_populate_smc_uvd_level()
1348 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT; in vegam_populate_smc_uvd_level()
1352 table->UvdLevel[count].VclkFrequency, &dividers); in vegam_populate_smc_uvd_level()
1356 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider; in vegam_populate_smc_uvd_level()
1359 table->UvdLevel[count].DclkFrequency, &dividers); in vegam_populate_smc_uvd_level()
1363 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider; in vegam_populate_smc_uvd_level()
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Dfiji_smumgr.c1582 table->UvdLevel[count].MinVoltage = 0; in fiji_populate_smc_uvd_level()
1583 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk; in fiji_populate_smc_uvd_level()
1584 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk; in fiji_populate_smc_uvd_level()
1585 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc * in fiji_populate_smc_uvd_level()
1587 table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc - in fiji_populate_smc_uvd_level()
1589 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT; in fiji_populate_smc_uvd_level()
1593 table->UvdLevel[count].VclkFrequency, &dividers); in fiji_populate_smc_uvd_level()
1597 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider; in fiji_populate_smc_uvd_level()
1600 table->UvdLevel[count].DclkFrequency, &dividers); in fiji_populate_smc_uvd_level()
1604 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider; in fiji_populate_smc_uvd_level()
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Dpolaris10_smumgr.c1407 table->UvdLevel[count].MinVoltage = 0; in polaris10_populate_smc_uvd_level()
1408 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk; in polaris10_populate_smc_uvd_level()
1409 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk; in polaris10_populate_smc_uvd_level()
1410 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc * in polaris10_populate_smc_uvd_level()
1421 table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT; in polaris10_populate_smc_uvd_level()
1422 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT; in polaris10_populate_smc_uvd_level()
1426 table->UvdLevel[count].VclkFrequency, &dividers); in polaris10_populate_smc_uvd_level()
1430 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider; in polaris10_populate_smc_uvd_level()
1433 table->UvdLevel[count].DclkFrequency, &dividers); in polaris10_populate_smc_uvd_level()
1437 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider; in polaris10_populate_smc_uvd_level()
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Dtonga_smumgr.c1313 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk; in tonga_populate_smc_uvd_level()
1314 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk; in tonga_populate_smc_uvd_level()
1315 table->UvdLevel[count].MinVoltage.Vddc = in tonga_populate_smc_uvd_level()
1318 table->UvdLevel[count].MinVoltage.VddGfx = in tonga_populate_smc_uvd_level()
1322 table->UvdLevel[count].MinVoltage.Vddci = in tonga_populate_smc_uvd_level()
1325 table->UvdLevel[count].MinVoltage.Phases = 1; in tonga_populate_smc_uvd_level()
1330 table->UvdLevel[count].VclkFrequency, in tonga_populate_smc_uvd_level()
1337 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider; in tonga_populate_smc_uvd_level()
1340 table->UvdLevel[count].DclkFrequency, &dividers); in tonga_populate_smc_uvd_level()
1345 table->UvdLevel[count].DclkDivider = in tonga_populate_smc_uvd_level()
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Dci_smumgr.c1526 table->UvdLevel[count].VclkFrequency = in ci_populate_smc_uvd_level()
1528 table->UvdLevel[count].DclkFrequency = in ci_populate_smc_uvd_level()
1530 table->UvdLevel[count].MinVddc = in ci_populate_smc_uvd_level()
1532 table->UvdLevel[count].MinVddcPhases = 1; in ci_populate_smc_uvd_level()
1535 table->UvdLevel[count].VclkFrequency, &dividers); in ci_populate_smc_uvd_level()
1539 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider; in ci_populate_smc_uvd_level()
1542 table->UvdLevel[count].DclkFrequency, &dividers); in ci_populate_smc_uvd_level()
1546 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider; in ci_populate_smc_uvd_level()
1547 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency); in ci_populate_smc_uvd_level()
1548 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency); in ci_populate_smc_uvd_level()
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/Linux-v4.19/drivers/gpu/drm/radeon/
Dsmu7_fusion.h235 SMU7_Fusion_UvdLevel UvdLevel [SMU7_MAX_LEVELS_UVD]; member
Dci_dpm.c2657 table->UvdLevel[count].VclkFrequency = in ci_populate_smc_uvd_level()
2659 table->UvdLevel[count].DclkFrequency = in ci_populate_smc_uvd_level()
2661 table->UvdLevel[count].MinVddc = in ci_populate_smc_uvd_level()
2663 table->UvdLevel[count].MinVddcPhases = 1; in ci_populate_smc_uvd_level()
2667 table->UvdLevel[count].VclkFrequency, false, &dividers); in ci_populate_smc_uvd_level()
2671 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2675 table->UvdLevel[count].DclkFrequency, false, &dividers); in ci_populate_smc_uvd_level()
2679 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2681 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency); in ci_populate_smc_uvd_level()
2682 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency); in ci_populate_smc_uvd_level()
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Dsmu7_discrete.h327 SMU7_Discrete_UvdLevel UvdLevel [SMU7_MAX_LEVELS_UVD]; member
Dkv_dpm.c879 offsetof(SMU7_Fusion_DpmTable, UvdLevel), in kv_populate_uvd_table()
/Linux-v4.19/drivers/gpu/drm/amd/powerplay/inc/
Dsmu7_fusion.h235 SMU7_Fusion_UvdLevel UvdLevel [SMU7_MAX_LEVELS_UVD]; member
Dsmu7_discrete.h328 SMU7_Discrete_UvdLevel UvdLevel [SMU7_MAX_LEVELS_UVD]; member
Dsmu72_discrete.h270 SMU72_Discrete_UvdLevel UvdLevel[SMU72_MAX_LEVELS_UVD]; member
Dsmu73_discrete.h254 SMU73_Discrete_UvdLevel UvdLevel [SMU73_MAX_LEVELS_UVD]; member
Dsmu74_discrete.h286 SMU74_Discrete_UvdLevel UvdLevel[SMU74_MAX_LEVELS_UVD]; member
Dsmu75_discrete.h292 SMU75_Discrete_UvdLevel UvdLevel [SMU75_MAX_LEVELS_UVD]; member
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dci_dpm.c2795 table->UvdLevel[count].VclkFrequency = in ci_populate_smc_uvd_level()
2797 table->UvdLevel[count].DclkFrequency = in ci_populate_smc_uvd_level()
2799 table->UvdLevel[count].MinVddc = in ci_populate_smc_uvd_level()
2801 table->UvdLevel[count].MinVddcPhases = 1; in ci_populate_smc_uvd_level()
2805 table->UvdLevel[count].VclkFrequency, false, &dividers); in ci_populate_smc_uvd_level()
2809 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2813 table->UvdLevel[count].DclkFrequency, false, &dividers); in ci_populate_smc_uvd_level()
2817 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2819 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency); in ci_populate_smc_uvd_level()
2820 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency); in ci_populate_smc_uvd_level()
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Dkv_dpm.c964 offsetof(SMU7_Fusion_DpmTable, UvdLevel), in kv_populate_uvd_table()