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Searched refs:TLBTEMP_BASE_1 (Results 1 – 6 of 6) sorted by relevance

/Linux-v4.19/arch/xtensa/mm/
Dcache.c71 kvaddr = TLBTEMP_BASE_1 + in kmap_invalidate_coherent()
95 void *kvaddr = coherent_kvaddr(page, TLBTEMP_BASE_1, vaddr, &paddr); in clear_user_highpage()
109 void *dst_vaddr = coherent_kvaddr(dst, TLBTEMP_BASE_1, vaddr, in copy_user_highpage()
160 virt = TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK); in flush_dcache_page()
163 virt = TLBTEMP_BASE_1 + (temp & DCACHE_ALIAS_MASK); in flush_dcache_page()
201 unsigned long virt = TLBTEMP_BASE_1 + (address & DCACHE_ALIAS_MASK); in local_flush_cache_page()
231 tmp = TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK); in update_mmu_cache()
233 tmp = TLBTEMP_BASE_1 + (addr & DCACHE_ALIAS_MASK); in update_mmu_cache()
268 unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK); in copy_to_user_page()
282 unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK); in copy_to_user_page()
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/Linux-v4.19/Documentation/xtensa/
Dmmu.txt79 | Cache aliasing | TLBTEMP_BASE_1 0xc7ff0000 DCACHE_WAY_SIZE
121 | Cache aliasing | TLBTEMP_BASE_1 0xa7ff0000 DCACHE_WAY_SIZE
164 | Cache aliasing | TLBTEMP_BASE_1 0x97ff0000 DCACHE_WAY_SIZE
/Linux-v4.19/arch/xtensa/include/asm/
Dfixmap.h66 TLBTEMP_BASE_1 + TLBTEMP_SIZE); in fix_to_virt()
Dhighmem.h75 TLBTEMP_BASE_1 + TLBTEMP_SIZE); in kmap()
Dpgtable.h76 #define TLBTEMP_BASE_1 (VMALLOC_END + 1) macro
77 #define TLBTEMP_BASE_2 (TLBTEMP_BASE_1 + DCACHE_WAY_SIZE)
/Linux-v4.19/arch/xtensa/kernel/
Dentry.S1699 movi a3, TLBTEMP_BASE_1