Searched refs:STMP_OFFSET_REG_CLR (Results 1 – 10 of 10) sorted by relevance
110 ts->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR); in mxs_lradc_map_ts_channel()134 ts->base + LRADC_CH(ch) + STMP_OFFSET_REG_CLR); in mxs_lradc_setup_ts_channel()150 ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_setup_ts_channel()192 ts->base + LRADC_CH(ch1) + STMP_OFFSET_REG_CLR); in mxs_lradc_setup_ts_pressure()194 ts->base + LRADC_CH(ch2) + STMP_OFFSET_REG_CLR); in mxs_lradc_setup_ts_pressure()204 ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_setup_ts_pressure()292 ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_setup_touch_detection()314 ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_prepare_x_pos()340 ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_prepare_y_pos()366 ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_prepare_pressure()[all …]
98 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR); in stmp3xxx_wdt_set_timeout()100 rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_CLR); in stmp3xxx_wdt_set_timeout()183 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR); in stmp3xxx_rtc_interrupt()206 STMP_OFFSET_REG_CLR); in stmp3xxx_alarm_irq_enable()208 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR); in stmp3xxx_alarm_irq_enable()251 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR); in stmp3xxx_rtc_remove()358 rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR); in stmp3xxx_rtc_probe()362 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR); in stmp3xxx_rtc_probe()395 rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR); in stmp3xxx_rtc_resume()
165 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()166 writel(0x1, adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()174 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()178 adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()201 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()414 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_handle_irq()449 const u32 st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR; in mxs_lradc_adc_configure_trigger()503 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_buffer_preenable()505 adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_buffer_preenable()517 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_buffer_preenable()[all …]
34 writel(mask, addr + STMP_OFFSET_REG_CLR); in stmp_clear_poll_bit()53 writel(STMP_MODULE_CLKGATE, reset_addr + STMP_OFFSET_REG_CLR); in stmp_reset_block()
16 #define STMP_OFFSET_REG_CLR 0x8 macro
305 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_spi_txrx_pio()314 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_spi_txrx_pio()323 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_spi_txrx_pio()371 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_spi_transfer_one()397 STMP_OFFSET_REG_CLR); in mxs_spi_transfer_one()
79 writel(BM_OCOTP_CTRL_ERROR, otp->base + STMP_OFFSET_REG_CLR); in mxs_ocotp_read()109 writel(BM_OCOTP_CTRL_RD_BANK_OPEN, otp->base + STMP_OFFSET_REG_CLR); in mxs_ocotp_read()
71 HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR); in timrot_irq_disable()83 HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR); in timrot_irq_acknowledge()
307 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_dma_resume_chan()310 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_CLR); in mxs_dma_resume_chan()356 mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_dma_int_handler()371 mxs_dma->base + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR); in mxs_dma_int_handler()
202 ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR); in mxs_mmc_irq_handler()541 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_mmc_enable_sdio_irq()543 ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR); in mxs_mmc_enable_sdio_irq()
