Lines Matching refs:STMP_OFFSET_REG_CLR

165 		       adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_read_single()
166 	writel(0x1, adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_read_single()
174 		       adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_read_single()
178 	       adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_read_single()
201 	       adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_read_single()
414 	       adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_handle_irq()
449 	const u32 st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;  in mxs_lradc_adc_configure_trigger()
503 		       adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_buffer_preenable()
505 	       adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_buffer_preenable()
517 	       adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_buffer_preenable()
518 	writel(ctrl4_clr, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_buffer_preenable()
533 	       adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_buffer_postdisable()
536 	       adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_buffer_postdisable()
539 		       adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_buffer_postdisable()