Home
last modified time | relevance | path

Searched refs:SSPP_DMA0 (Results 1 – 8 of 8) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_cfg.c37 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
121 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
205 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
298 [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
367 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
Dmdp5_ctl.c304 case SSPP_DMA0: return MDP5_CTL_LAYER_REG_DMA0(stage); in mdp_ctl_blend_mask()
327 case SSPP_DMA0: return MDP5_CTL_LAYER_EXT_REG_DMA0_BIT3; in mdp_ctl_blend_ext_mask()
455 case SSPP_DMA0: return MDP5_CTL_FLUSH_DMA0; in mdp_ctl_flush_mask_pipe()
Dmdp5.xml.h75 SSPP_DMA0 = 7, enumerator
545 case SSPP_DMA0: return (mdp5_cfg->pipe_dma.base[0]); in __offset_PIPE()
Dmdp5_kms.c818 SSPP_DMA0, SSPP_DMA1, in hwpipe_init() enumerator
/Linux-v4.19/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_top.c173 status->sspp[SSPP_DMA0] = (value >> 20) & 0x3; in dpu_hw_get_danger_status()
270 status->sspp[SSPP_DMA0] = (value >> 20) & 0x1; in dpu_hw_get_safe_status()
Ddpu_hw_ctl.c147 case SSPP_DMA0: in dpu_hw_ctl_get_bitmask_sspp()
389 case SSPP_DMA0: in dpu_hw_ctl_setup_blendstage()
Ddpu_hw_mdss.h125 SSPP_DMA0, enumerator
Ddpu_hw_catalog.c208 SSPP_DMA_BLK("sspp_8", SSPP_DMA0, 0x24000,