| /Linux-v4.19/include/dt-bindings/clock/ |
| D | rk3036-cru.h | 33 #define SCLK_UART1 78 macro
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| D | exynos7-clk.h | 99 #define SCLK_UART1 4 macro
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| D | s5pv210.h | 199 #define SCLK_UART1 174 macro
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| D | rk3188-cru-common.h | 30 #define SCLK_UART1 65 macro
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| D | rk3128-cru.h | 35 #define SCLK_UART1 78 macro
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| D | rk3228-cru.h | 34 #define SCLK_UART1 78 macro
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| D | rv1108-cru.h | 32 #define SCLK_UART1 73 macro
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| D | px30-cru.h | 26 #define SCLK_UART1 24 macro
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| D | rk3288-cru.h | 42 #define SCLK_UART1 78 macro
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| D | rk3328-cru.h | 37 #define SCLK_UART1 39 macro
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| D | rk3368-cru.h | 40 #define SCLK_UART1 78 macro
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| D | rk3399-cru.h | 48 #define SCLK_UART1 82 macro
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| /Linux-v4.19/drivers/clk/rockchip/ |
| D | clk-rk3036.c | 160 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
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| D | clk-rk3128.c | 197 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
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| D | clk-rk3228.c | 212 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
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| D | clk-rk3188.c | 270 MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, 0,
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| D | clk-rk3328.c | 264 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
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| D | clk-rv1108.c | 180 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
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| D | clk-rk3368.c | 269 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
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| D | clk-rk3288.c | 249 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
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| /Linux-v4.19/arch/arm/boot/dts/ |
| D | rk3xxx.dtsi | 146 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
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| D | s5pv210.dtsi | 348 <&clocks SCLK_UART1>;
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| /Linux-v4.19/drivers/clk/samsung/ |
| D | clk-s5pv210.c | 639 GATE(SCLK_UART1, "sclk_uart1", "dout_uart1", CLK_SRC_MASK0, 13,
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| D | clk-exynos7.c | 777 GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
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| /Linux-v4.19/arch/arm64/boot/dts/exynos/ |
| D | exynos7.dtsi | 232 <&clock_peric1 SCLK_UART1>;
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