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Searched refs:RREG32_SMC (Results 1 – 25 of 28) sorted by relevance

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/Linux-v4.19/drivers/gpu/drm/radeon/
Dci_smc.c116 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in ci_start_smc()
124 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in ci_reset_smc()
139 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in ci_stop_smc_clock()
148 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in ci_start_smc_clock()
157 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in ci_is_smc_running()
158 u32 pc_c = RREG32_SMC(SMC_PC_C); in ci_is_smc_running()
176 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
Dsi_smc.c115 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in si_start_smc()
131 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in si_reset_smc()
145 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_stop_smc_clock()
154 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_start_smc_clock()
163 u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in si_is_smc_running()
164 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_is_smc_running()
202 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_wait_for_smc_inactive()
Dtrinity_dpm.c377 value = RREG32_SMC(GFX_POWER_GATING_CNTL); in trinity_gfx_powergating_initialize()
505 if (RREG32_SMC(CC_SMU_TST_EFUSE1_MISC) & RB_BACKEND_DISABLE_MASK) in trinity_gfx_powergating_enable()
506 WREG32_SMC(SMU_SCRATCH_A, (RREG32_SMC(SMU_SCRATCH_A) | 0x01)); in trinity_gfx_powergating_enable()
521 value = RREG32_SMC(PM_I_CNTL_1); in trinity_gfx_dynamic_mgpg_enable()
526 value = RREG32_SMC(SMU_S_PG_CNTL); in trinity_gfx_dynamic_mgpg_enable()
531 value = RREG32_SMC(SMU_S_PG_CNTL); in trinity_gfx_dynamic_mgpg_enable()
535 value = RREG32_SMC(PM_I_CNTL_1); in trinity_gfx_dynamic_mgpg_enable()
595 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix); in trinity_set_divider_value()
605 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix); in trinity_set_divider_value()
617 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); in trinity_set_ds_dividers()
[all …]
Dci_dpm.c582 data = RREG32_SMC(config_regs->offset); in ci_program_pt_config_registers()
884 tmp = RREG32_SMC(CG_THERMAL_INT); in ci_thermal_set_temperature_range()
892 tmp = RREG32_SMC(CG_THERMAL_CTRL); in ci_thermal_set_temperature_range()
907 u32 thermal_int = RREG32_SMC(CG_THERMAL_INT); in ci_thermal_enable_alert()
939 tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; in ci_fan_ctrl_set_static_mode()
941 tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; in ci_fan_ctrl_set_static_mode()
946 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK; in ci_fan_ctrl_set_static_mode()
950 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; in ci_fan_ctrl_set_static_mode()
971 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; in ci_thermal_setup_fan_table()
1015 tmp = (RREG32_SMC(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; in ci_thermal_setup_fan_table()
[all …]
Dkv_smc.c61 *enable_mask = RREG32_SMC(SMC_SYSCON_MSG_ARG_0); in kv_dpm_get_enable_mask()
Dkv_dpm.c298 data = RREG32_SMC(config_regs->offset); in kv_program_pt_config_registers()
645 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); in kv_start_dpm()
660 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); in kv_start_am()
670 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); in kv_reset_am()
1176 thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL); in kv_enable_thermal_int()
2440 nbdpmconfig1 = RREG32_SMC(NB_DPM_CONFIG_1); in kv_program_nbps_index_settings()
2467 tmp = RREG32_SMC(CG_THERMAL_INT_CTRL); in kv_set_thermal_temperature_range()
2805 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >> in kv_dpm_debugfs_print_current_performance_level()
2814 tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >> in kv_dpm_debugfs_print_current_performance_level()
2828 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >> in kv_dpm_get_current_sclk()
Dcik.c212 temp = (RREG32_SMC(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >> in ci_get_temp()
231 temp = RREG32_SMC(0xC0300E0C); in kv_get_temp()
1719 if (RREG32_SMC(GENERAL_PWRMGT) & GPU_COUNTER_CLK) in cik_get_xclk()
1722 if (RREG32_SMC(CG_CLKPIN_CNTL) & XTALIN_DIVIDE) in cik_get_xclk()
9436 tmp = RREG32_SMC(cntl_reg); in cik_set_uvd_clock()
9442 if (RREG32_SMC(status_reg) & DCLK_STATUS) in cik_set_uvd_clock()
9476 if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS) in cik_set_vce_clocks()
9483 tmp = RREG32_SMC(CG_ECLK_CNTL); in cik_set_vce_clocks()
9489 if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS) in cik_set_vce_clocks()
9757 orig = data = RREG32_SMC(THM_CLK_CNTL); in cik_program_aspm()
[all …]
Dradeon.h2536 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) macro
2568 uint32_t tmp_ = RREG32_SMC(reg); \
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dci_smc.c119 u32 tmp = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); in amdgpu_ci_start_smc()
127 u32 tmp = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); in amdgpu_ci_reset_smc()
142 u32 tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); in amdgpu_ci_stop_smc_clock()
151 u32 tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); in amdgpu_ci_start_smc_clock()
160 u32 clk = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); in amdgpu_ci_is_smc_running()
161 u32 pc_c = RREG32_SMC(ixSMC_PC_C); in amdgpu_ci_is_smc_running()
199 tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); in amdgpu_ci_wait_for_smc_inactive()
Dsi_smc.c113 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in amdgpu_si_start_smc()
129 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL) | in amdgpu_si_reset_smc()
143 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in amdgpu_si_smc_clock()
155 u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in amdgpu_si_is_smc_running()
156 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in amdgpu_si_is_smc_running()
194 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in amdgpu_si_wait_for_smc_inactive()
Dcik.c845 if (RREG32_SMC(ixGENERAL_PWRMGT) & GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK) in cik_get_xclk()
848 if (RREG32_SMC(ixCG_CLKPIN_CNTL) & CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK) in cik_get_xclk()
905 rom_cntl = RREG32_SMC(ixROM_CNTL); in cik_read_disabled_bios()
1311 tmp = RREG32_SMC(cntl_reg); in cik_set_uvd_clock()
1318 if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK) in cik_set_uvd_clock()
1353 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK) in cik_set_vce_clocks()
1360 tmp = RREG32_SMC(ixCG_ECLK_CNTL); in cik_set_vce_clocks()
1367 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK) in cik_set_vce_clocks()
1644 orig = data = RREG32_SMC(ixTHM_CLK_CNTL); in cik_program_aspm()
1652 orig = data = RREG32_SMC(ixMISC_CLK_CTRL); in cik_program_aspm()
[all …]
Dci_dpm.c707 data = RREG32_SMC(config_regs->offset); in ci_program_pt_config_registers()
1022 tmp = RREG32_SMC(ixCG_THERMAL_INT); in ci_thermal_set_temperature_range()
1030 tmp = RREG32_SMC(ixCG_THERMAL_CTRL); in ci_thermal_set_temperature_range()
1044 u32 thermal_int = RREG32_SMC(ixCG_THERMAL_INT); in ci_thermal_enable_alert()
1076 tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK) in ci_fan_ctrl_set_static_mode()
1079 tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK) in ci_fan_ctrl_set_static_mode()
1085 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK; in ci_fan_ctrl_set_static_mode()
1089 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK; in ci_fan_ctrl_set_static_mode()
1110 duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) in ci_thermal_setup_fan_table()
1155 tmp = (RREG32_SMC(ixCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK) in ci_thermal_setup_fan_table()
[all …]
Dvi.c334 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2); in vi_get_xclk()
338 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL); in vi_get_xclk()
389 rom_cntl = RREG32_SMC(ixROM_CNTL); in vi_read_disabled_bios()
731 tmp = RREG32_SMC(cntl_reg); in vi_set_uvd_clock()
742 tmp = RREG32_SMC(status_reg); in vi_set_uvd_clock()
818 if (RREG32_SMC(reg_status) & status_mask) in vi_set_vce_clocks()
826 tmp = RREG32_SMC(reg_ctrl); in vi_set_vce_clocks()
832 if (RREG32_SMC(reg_status) & status_mask) in vi_set_vce_clocks()
895 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK) in vi_get_rev_id()
1344 temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0); in vi_update_rom_medium_grain_clock_gating()
[all …]
Dvce_v3_0.c374 tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) & in vce_v3_0_get_harvest_config()
378 tmp = (RREG32_SMC(ixCC_HARVEST_FUSES) & in vce_v3_0_get_harvest_config()
820 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU); in vce_v3_0_get_clockgating_state()
822 data = RREG32_SMC(ixCURRENT_PG_STATUS); in vce_v3_0_get_clockgating_state()
Dkv_dpm.c427 data = RREG32_SMC(config_regs->offset); in kv_program_pt_config_registers()
728 u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT); in kv_start_dpm()
743 u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL); in kv_start_am()
754 u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL); in kv_reset_am()
2508 nbdpmconfig1 = RREG32_SMC(ixNB_DPM_CONFIG_1); in kv_program_nbps_index_settings()
2537 tmp = RREG32_SMC(ixCG_THERMAL_INT_CTRL); in kv_set_thermal_temperature_range()
2871 (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) & in kv_dpm_debugfs_print_current_performance_level()
2881 tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) & in kv_dpm_debugfs_print_current_performance_level()
2956 temp = RREG32_SMC(0xC0300E0C); in kv_dpm_get_temp()
3150 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL); in kv_dpm_set_interrupt_state()
[all …]
Dkv_smc.c64 *enable_mask = RREG32_SMC(ixSMC_SYSCON_MSG_ARG_0); in amdgpu_kv_dpm_get_enable_mask()
Duvd_v4_2.c709 if (!(RREG32_SMC(ixCURRENT_PG_STATUS) & in uvd_v4_2_set_powergating_state()
720 if (RREG32_SMC(ixCURRENT_PG_STATUS) & in uvd_v4_2_set_powergating_state()
Duvd_v6_0.c374 (RREG32_SMC(ixCC_HARVEST_FUSES) & CC_HARVEST_FUSES__UVD_DISABLE_MASK)) in uvd_v6_0_early_init()
1488 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU); in uvd_v6_0_get_clockgating_state()
1490 data = RREG32_SMC(ixCURRENT_PG_STATUS); in uvd_v6_0_get_clockgating_state()
Damdgpu_cgs.c67 return RREG32_SMC(index); in amdgpu_cgs_read_ind_register()
Duvd_v5_0.c825 if (RREG32_SMC(ixCURRENT_PG_STATUS) & in uvd_v5_0_get_clockgating_state()
Damdgpu_debugfs.c400 value = RREG32_SMC(*pos); in amdgpu_debugfs_regs_smc_read()
Dvce_v4_0.c870 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
Dsi_dpm.c2849 data = RREG32_SMC(offset); in si_program_cac_config_registers()
7512 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); in si_dpm_set_interrupt_state()
7517 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); in si_dpm_set_interrupt_state()
7529 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); in si_dpm_set_interrupt_state()
7534 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); in si_dpm_set_interrupt_state()
Damdgpu.h1609 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) macro
Duvd_v7_0.c1677 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);

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