582 				data = RREG32_SMC(config_regs->offset);  in ci_program_pt_config_registers()
884 	tmp = RREG32_SMC(CG_THERMAL_INT);  in ci_thermal_set_temperature_range()
892 	tmp = RREG32_SMC(CG_THERMAL_CTRL);  in ci_thermal_set_temperature_range()
907 	u32 thermal_int = RREG32_SMC(CG_THERMAL_INT);  in ci_thermal_enable_alert()
939 		tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;  in ci_fan_ctrl_set_static_mode()
941 		tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;  in ci_fan_ctrl_set_static_mode()
946 	tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;  in ci_fan_ctrl_set_static_mode()
950 	tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;  in ci_fan_ctrl_set_static_mode()
971 	duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;  in ci_thermal_setup_fan_table()
1015 	tmp = (RREG32_SMC(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;  in ci_thermal_setup_fan_table()
1082 	duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;  in ci_fan_ctrl_get_fan_speed_percent()
1083 	duty = (RREG32_SMC(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;  in ci_fan_ctrl_get_fan_speed_percent()
1115 	duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;  in ci_fan_ctrl_set_fan_speed_percent()
1124 	tmp = RREG32_SMC(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;  in ci_fan_ctrl_set_fan_speed_percent()
1155 	tmp = RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;  in ci_fan_ctrl_get_mode()
1172 	tach_period = (RREG32_SMC(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
1201 	tmp = RREG32_SMC(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
1217 		tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;  in ci_fan_ctrl_set_default_mode()
1221 		tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;  in ci_fan_ctrl_set_default_mode()
1241 		tmp = RREG32_SMC(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;  in ci_thermal_initialize()
1246 	tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;  in ci_thermal_initialize()
1408 		tmp = RREG32_SMC(CG_THERMAL_CTRL);  in ci_set_dpm_event_sources()
1414 		tmp = RREG32_SMC(GENERAL_PWRMGT);  in ci_set_dpm_event_sources()
1421 		tmp = RREG32_SMC(GENERAL_PWRMGT);  in ci_set_dpm_event_sources()
1531 	tmp = RREG32_SMC(GENERAL_PWRMGT);  in ci_start_dpm()
1535 	tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);  in ci_start_dpm()
1592 	tmp = RREG32_SMC(GENERAL_PWRMGT);  in ci_stop_dpm()
1596 	tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);  in ci_stop_dpm()
1619 	u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);  in ci_enable_sclk_control()
1803 		if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED)  in ci_dpm_start_smc()
1873 		RREG32_SMC(CG_SPLL_FUNC_CNTL);  in ci_read_clock_registers()
1875 		RREG32_SMC(CG_SPLL_FUNC_CNTL_2);  in ci_read_clock_registers()
1877 		RREG32_SMC(CG_SPLL_FUNC_CNTL_3);  in ci_read_clock_registers()
1879 		RREG32_SMC(CG_SPLL_FUNC_CNTL_4);  in ci_read_clock_registers()
1881 		RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);  in ci_read_clock_registers()
1883 		RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2);  in ci_read_clock_registers()
1905 	u32 tmp = RREG32_SMC(GENERAL_PWRMGT);  in ci_enable_thermal_protection()
1916 	u32 tmp = RREG32_SMC(GENERAL_PWRMGT);  in ci_enable_acpi_power_management()
1985 	u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);  in ci_program_display_gap()
2024 			tmp = RREG32_SMC(GENERAL_PWRMGT);  in ci_enable_spread_spectrum()
2029 		tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);  in ci_enable_spread_spectrum()
2033 		tmp = RREG32_SMC(GENERAL_PWRMGT);  in ci_enable_spread_spectrum()
2046 	u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);  in ci_enable_display_gap()
2059 	tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);  in ci_program_vc()
2077 	tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);  in ci_clear_vc()
2097 		if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE)  in ci_upload_firmware()
2485 	tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8;  in ci_force_switch_to_arb_f0()
4088 		tmp = RREG32_SMC(DPM_TABLE_475);  in ci_update_uvd_dpm()
4126 			tmp = RREG32_SMC(DPM_TABLE_475);  in ci_update_vce_dpm()
4156 		tmp = RREG32_SMC(DPM_TABLE_475);
4223 					tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &  in ci_dpm_force_performance_level()
4242 					tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &  in ci_dpm_force_performance_level()
4261 					tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &  in ci_dpm_force_performance_level()
4278 				tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &  in ci_dpm_force_performance_level()
4293 				tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &  in ci_dpm_force_performance_level()
4308 				tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &  in ci_dpm_force_performance_level()
4789 	u32 tmp = RREG32_SMC(GENERAL_PWRMGT);  in ci_enable_voltage_control()
5844 		u32 tmp = RREG32_SMC(CNB_PWRMGT_CNTL);  in ci_dpm_init()