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Searched refs:REG_FLD_MOD (Results 1 – 22 of 22) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/omapdrm/dss/
Dhdmi5_core.c66 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); in hdmi_core_ddc_init()
72 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); in hdmi_core_ddc_init()
76 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, in hdmi_core_ddc_init()
78 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR, in hdmi_core_ddc_init()
83 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR, in hdmi_core_ddc_init()
85 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR, in hdmi_core_ddc_init()
90 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR, in hdmi_core_ddc_init()
92 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR, in hdmi_core_ddc_init()
97 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR, in hdmi_core_ddc_init()
99 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR, in hdmi_core_ddc_init()
[all …]
Dhdmi4_core.c51 REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0); in hdmi_core_ddc_init()
56 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0); in hdmi_core_ddc_init()
66 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0); in hdmi_core_ddc_init()
76 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0); in hdmi_core_ddc_init()
107 REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0); in hdmi_core_ddc_edid()
110 REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1); in hdmi_core_ddc_edid()
113 REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0); in hdmi_core_ddc_edid()
116 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0); in hdmi_core_ddc_edid()
117 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0); in hdmi_core_ddc_edid()
121 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0); in hdmi_core_ddc_edid()
[all …]
Dhdmi_phy.c122 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, lane_cfg_val, 26, 22); in hdmi_phy_configure_lanes()
123 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, pol_val, 30, 27); in hdmi_phy_configure_lanes()
142 REG_FLD_MOD(phy->base, HDMI_TXPHY_BIST_CONTROL, 1, 11, 11); in hdmi_phy_configure()
159 REG_FLD_MOD(phy->base, HDMI_TXPHY_TX_CTRL, freqout, 31, 30); in hdmi_phy_configure()
166 REG_FLD_MOD(phy->base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); in hdmi_phy_configure()
Ddss.c68 #define REG_FLD_MOD(dss, idx, val, start, end) \ macro
280 REG_FLD_MOD(dss, DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ in dss_sdi_enable()
284 REG_FLD_MOD(dss, DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ in dss_sdi_enable()
296 REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 28, 28); in dss_sdi_enable()
324 REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ in dss_sdi_enable()
338 REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ in dss_sdi_disable()
445 REG_FLD_MOD(dss, DSS_CONTROL, b, /* DISPC_CLK_SWITCH */ in dss_select_dispc_clk_source()
475 REG_FLD_MOD(dss, DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */ in dss_select_dsi_clk_source()
495 REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit); in dss_lcd_clk_mux_dra7()
503 REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit); in dss_lcd_clk_mux_dra7()
[all …]
Dhdmi4_cec.c120 REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7); in hdmi4_cec_irq()
128 REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7); in hdmi4_cec_irq()
140 REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7); in hdmi_cec_clear_tx_fifo()
175 REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0, 3, 3); in hdmi_cec_adap_enable()
206 REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0x1, 3, 3); in hdmi_cec_adap_enable()
285 REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, attempts - 1, 6, 4); in hdmi_cec_adap_transmit()
340 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0x18, 5, 0); in hdmi4_cec_init()
Dhdmi_wp.c77 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6); in hdmi_wp_set_phy_pwr()
93 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2); in hdmi_wp_set_pll_pwr()
107 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31); in hdmi_wp_video_start()
118 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31); in hdmi_wp_video_stop()
138 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode, in hdmi_wp_video_config_format()
269 REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31); in hdmi_wp_audio_enable()
276 REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30); in hdmi_wp_audio_core_req_enable()
Ddispc.c64 #define REG_FLD_MOD(dispc, idx, val, start, end) \ macro
396 REG_FLD_MOD(dispc, rfld.reg, val, rfld.high, rfld.low); in mgr_fld_write()
399 REG_FLD_MOD(dispc, rfld.reg, val, rfld.high, rfld.low); in mgr_fld_write()
769 REG_FLD_MOD(dispc, DISPC_CONTROL2, 1, 6, 6); in dispc_wb_go()
894 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); in dispc_ovl_write_color_conv_coef()
912 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); in dispc_wb_write_color_conv_coef()
1018 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26); in dispc_ovl_set_zorder()
1029 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); in dispc_ovl_enable_zorder_planes()
1040 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); in dispc_ovl_set_pre_mult_alpha()
1055 REG_FLD_MOD(dispc, DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); in dispc_ovl_setup_global_alpha()
[all …]
Dhdmi5.c109 REG_FLD_MOD(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15); in hdmi_irq_handler()
337 REG_FLD_MOD(hdmi->wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); in read_edid()
341 REG_FLD_MOD(hdmi->wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2); in read_edid()
351 REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); in hdmi_start_audio_stream()
360 REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2); in hdmi_stop_audio_stream()
Ddsi.c125 #define REG_FLD_MOD(dsi, idx, val, start, end) \ macro
1221 REG_FLD_MOD(dsi, DSI_CTRL, enable, 0, 0); /* IF_EN */ in dsi_if_enable()
1304 REG_FLD_MOD(dsi, DSI_CLK_CTRL, lp_clk_div, 12, 0); in dsi_set_lp_clk_divisor()
1307 REG_FLD_MOD(dsi, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); in dsi_set_lp_clk_divisor()
1315 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ in dsi_enable_scp_clk()
1322 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ in dsi_disable_scp_clk()
1342 REG_FLD_MOD(dsi, DSI_CLK_CTRL, state, 31, 30); in dsi_pll_power()
1735 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG1, state, 28, 27); in dsi_cio_power()
1957 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, l, lptxscp_start, 17); in dsi_cio_enable_lane_override()
1962 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 1, 27, 27); in dsi_cio_enable_lane_override()
[all …]
Dhdmi.h287 #define REG_FLD_MOD(base, idx, val, start, end) \ macro
/Linux-v4.19/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi5_core.c67 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); in hdmi_core_ddc_init()
73 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); in hdmi_core_ddc_init()
77 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, in hdmi_core_ddc_init()
79 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR, in hdmi_core_ddc_init()
84 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR, in hdmi_core_ddc_init()
86 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR, in hdmi_core_ddc_init()
91 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR, in hdmi_core_ddc_init()
93 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR, in hdmi_core_ddc_init()
98 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR, in hdmi_core_ddc_init()
100 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR, in hdmi_core_ddc_init()
[all …]
Dhdmi4_core.c52 REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0); in hdmi_core_ddc_init()
57 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0); in hdmi_core_ddc_init()
67 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0); in hdmi_core_ddc_init()
77 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0); in hdmi_core_ddc_init()
108 REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0); in hdmi_core_ddc_edid()
111 REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1); in hdmi_core_ddc_edid()
114 REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0); in hdmi_core_ddc_edid()
117 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0); in hdmi_core_ddc_edid()
118 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0); in hdmi_core_ddc_edid()
122 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0); in hdmi_core_ddc_edid()
[all …]
Dhdmi_phy.c131 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, lane_cfg_val, 26, 22); in hdmi_phy_configure_lanes()
132 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, pol_val, 30, 27); in hdmi_phy_configure_lanes()
151 REG_FLD_MOD(phy->base, HDMI_TXPHY_BIST_CONTROL, 1, 11, 11); in hdmi_phy_configure()
168 REG_FLD_MOD(phy->base, HDMI_TXPHY_TX_CTRL, freqout, 31, 30); in hdmi_phy_configure()
175 REG_FLD_MOD(phy->base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); in hdmi_phy_configure()
Ddss.c69 #define REG_FLD_MOD(idx, val, start, end) \ macro
296 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ in dss_sdi_enable()
300 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ in dss_sdi_enable()
312 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); in dss_sdi_enable()
340 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ in dss_sdi_enable()
354 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ in dss_sdi_disable()
428 REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */ in dss_select_dispc_clk_source()
456 REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */ in dss_select_dsi_clk_source()
491 REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */ in dss_select_lcd_clk_source()
627 REG_FLD_MOD(DSS_CONTROL, l, 6, 6); in dss_set_venc_output()
[all …]
Dhdmi_wp.c78 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6); in hdmi_wp_set_phy_pwr()
94 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2); in hdmi_wp_set_pll_pwr()
108 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31); in hdmi_wp_video_start()
119 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31); in hdmi_wp_video_stop()
139 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode, in hdmi_wp_video_config_format()
249 REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31); in hdmi_wp_audio_enable()
256 REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30); in hdmi_wp_audio_core_req_enable()
Ddispc.c62 #define REG_FLD_MOD(idx, val, start, end) \ macro
287 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low); in mgr_fld_write()
614 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6); in dispc_wb_go()
711 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); in dispc_ovl_write_color_conv_coef()
801 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26); in dispc_ovl_set_zorder()
812 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); in dispc_ovl_enable_zorder_planes()
821 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); in dispc_ovl_set_pre_mult_alpha()
834 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); in dispc_ovl_setup_global_alpha()
925 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); in dispc_ovl_set_color_mode()
935 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29); in dispc_ovl_configure_burst_type()
[all …]
Dhdmi5.c109 REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15); in hdmi_irq_handler()
330 REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); in read_edid()
334 REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2); in read_edid()
344 REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); in hdmi_start_audio_stream()
353 REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2); in hdmi_stop_audio_stream()
Ddsi.c124 #define REG_FLD_MOD(dsidev, idx, val, start, end) \ macro
1228 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */ in dsi_if_enable()
1317 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0); in dsi_set_lp_clk_divisor()
1320 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); in dsi_set_lp_clk_divisor()
1330 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ in dsi_enable_scp_clk()
1339 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ in dsi_disable_scp_clk()
1360 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30); in dsi_pll_power()
1759 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27); in dsi_cio_power()
1984 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17); in dsi_cio_enable_lane_override()
1989 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27); in dsi_cio_enable_lane_override()
[all …]
Drfbi.c70 #define REG_FLD_MOD(idx, val, start, end) \ macro
346 REG_FLD_MOD(RFBI_CONTROL, 0, 0, 0); in framedone_callback()
458 REG_FLD_MOD(RFBI_CONFIG(rfbi_module), in rfbi_set_timings()
730 REG_FLD_MOD(RFBI_CONTROL, 0, 3, 2); /* clear CS */ in rfbi_configure_bus()
Dhdmi.h269 #define REG_FLD_MOD(base, idx, val, start, end) \ macro
/Linux-v4.19/drivers/gpu/drm/gma500/
Dmdfld_dsi_dpi.c113 REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), !!state, 0, 0); in dsi_set_device_ready_state()
146 REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 2, 2, 1); in dsi_set_pipe_plane_enable_state()
150 REG_FLD_MOD(MIPI_PORT_CONTROL(pipe), 0, 16, 16); in dsi_set_pipe_plane_enable_state()
154 REG_FLD_MOD(dspcntr_reg, 0, 31, 31); in dsi_set_pipe_plane_enable_state()
161 REG_FLD_MOD(pipeconf_reg, 0, 31, 31); in dsi_set_pipe_plane_enable_state()
476 REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 0, 0, 0); in mdfld_dsi_dpi_controller_init()
565 REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 1, 0, 0); in mdfld_dsi_dpi_controller_init()
Dmdfld_dsi_output.h50 #define REG_FLD_MOD(reg, val, start, end) \ macro