64 #define REG_FLD_MOD(dispc, idx, val, start, end)			\  macro
396 		REG_FLD_MOD(dispc, rfld.reg, val, rfld.high, rfld.low);  in mgr_fld_write()
399 		REG_FLD_MOD(dispc, rfld.reg, val, rfld.high, rfld.low);  in mgr_fld_write()
769 	REG_FLD_MOD(dispc, DISPC_CONTROL2, 1, 6, 6);  in dispc_wb_go()
894 	REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);  in dispc_ovl_write_color_conv_coef()
912 	REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);  in dispc_wb_write_color_conv_coef()
1018 	REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);  in dispc_ovl_set_zorder()
1029 		REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);  in dispc_ovl_enable_zorder_planes()
1040 	REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);  in dispc_ovl_set_pre_mult_alpha()
1055 	REG_FLD_MOD(dispc, DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);  in dispc_ovl_setup_global_alpha()
1140 	REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);  in dispc_ovl_set_color_mode()
1163 		REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);  in dispc_ovl_configure_burst_type()
1165 		REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);  in dispc_ovl_configure_burst_type()
1280 	REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), burst_size,  in dispc_ovl_set_burst_size()
1379 	REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);  in dispc_ovl_enable_replication()
1533 	REG_FLD_MOD(dispc, DISPC_CONFIG, enable ? 1 : 0, 14, 14);  in dispc_enable_fifomerge()
1593 	REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);  in dispc_ovl_set_mflag()
1920 			REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane),  in dispc_ovl_set_scaling_uv()
1973 		REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane),  in dispc_ovl_set_scaling_uv()
1977 	REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);  in dispc_ovl_set_scaling_uv()
1979 	REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);  in dispc_ovl_set_scaling_uv()
2058 	REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);  in dispc_ovl_set_rotation_attrs()
2060 		REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane),  in dispc_ovl_set_rotation_attrs()
2070 		REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane),  in dispc_ovl_set_rotation_attrs()
2870 		REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0);  in dispc_wb_setup()
2886 		REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0);  in dispc_wb_setup()
2902 	REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);  in dispc_ovl_enable()
2920 	REG_FLD_MOD(dispc, DISPC_CONTROL, act_high ? 1 : 0, 29, 29);  in dispc_lcd_enable_signal_polarity()
2928 	REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 28, 28);  in dispc_lcd_enable_signal()
2936 	REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 27, 27);  in dispc_pck_free_enable()
2956 	REG_FLD_MOD(dispc, DISPC_CONFIG, mode, 2, 1);  in dispc_set_loadmode()
2990 		REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 18, 18);  in dispc_mgr_enable_alpha_fixed_zorder()
2992 		REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 19, 19);  in dispc_mgr_enable_alpha_fixed_zorder()
3277 			REG_FLD_MOD(dispc, DISPC_CONTROL,  in dispc_mgr_set_timings()
3806 	REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 2, 4, 3);  in dispc_enable_sidle()
3811 	REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 1, 4, 3);	/* SIDLEMODE: no idle */  in dispc_disable_sidle()
3965 		REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 3, 3);  in _omap_dispc_initial_config()
3973 		REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 9, 9);  in _omap_dispc_initial_config()
3986 		REG_FLD_MOD(dispc, DISPC_MSTANDBY_CTRL, 1, 0, 0);  in _omap_dispc_initial_config()
4678 	REG_FLD_MOD(dispc, DISPC_CONFIG, 0x1f, 8, 4);  in dispc_errata_i734_wa()
4716 	REG_FLD_MOD(dispc, DISPC_CONFIG, gatestate, 8, 4);  in dispc_errata_i734_wa()