Searched refs:RD_REG_DWORD (Results 1 – 14 of 14) sorted by relevance
150 stat = RD_REG_DWORD(®->host_status); in qla27xx_dump_mpi_ram()164 RD_REG_DWORD(®->hccr); in qla27xx_dump_mpi_ram()170 RD_REG_DWORD(®->hccr); in qla27xx_dump_mpi_ram()228 stat = RD_REG_DWORD(®->host_status); in qla24xx_dump_ram()241 RD_REG_DWORD(®->hccr); in qla24xx_dump_ram()247 RD_REG_DWORD(®->hccr); in qla24xx_dump_ram()298 *buf++ = htonl(RD_REG_DWORD(dmp_reg)); in qla24xx_read_window()310 if (RD_REG_DWORD(®->host_status) & HSRX_RISC_PAUSED) in qla24xx_pause_risc()329 if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) in qla24xx_soft_reset()334 if (!(RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE)) in qla24xx_soft_reset()[all …]
684 RD_REG_DWORD(®->rsp_q_out); in qlafx00_config_rings()915 pseudo_aen = RD_REG_DWORD(®->pseudoaen); in qlafx00_init_fw_ready()917 aenmbx7 = RD_REG_DWORD(®->initval7); in qlafx00_init_fw_ready()928 aenmbx = RD_REG_DWORD(®->aenmailbox0); in qlafx00_init_fw_ready()947 aenmbx7 = RD_REG_DWORD(®->aenmailbox7); in qlafx00_init_fw_ready()950 ha->req_que_off = RD_REG_DWORD(®->aenmailbox1); in qlafx00_init_fw_ready()951 ha->rsp_que_off = RD_REG_DWORD(®->aenmailbox3); in qlafx00_init_fw_ready()952 ha->req_que_len = RD_REG_DWORD(®->aenmailbox5); in qlafx00_init_fw_ready()953 ha->rsp_que_len = RD_REG_DWORD(®->aenmailbox6); in qlafx00_init_fw_ready()985 aenmbx7 = RD_REG_DWORD(®->initval7); in qlafx00_init_fw_ready()[all …]
371 RD_REG_DWORD((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG)381 RD_REG_DWORD((ha)->cregbase + off)387 RD_REG_DWORD((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG)400 RD_REG_DWORD((ha)->cregbase + off)
464 (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) == 0 && in qla24xx_read_flash_dword()476 data = RD_REG_DWORD(®->flash_data); in qla24xx_read_flash_dword()504 RD_REG_DWORD(®->flash_data); /* PCI Posting. */ in qla24xx_write_flash_dword()508 for (cnt = 500000; (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) && in qla24xx_write_flash_dword()1174 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); in qla24xx_unprotect_flash()1175 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ in qla24xx_unprotect_flash()1213 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); in qla24xx_protect_flash()1214 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ in qla24xx_protect_flash()1441 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); in qla24xx_write_nvram_data()1442 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ in qla24xx_write_nvram_data()[all …]
372 win_read = RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase); in qla82xx_pci_set_crbwindow_2M()522 data = RD_REG_DWORD(off); in qla82xx_rd_32()941 RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase); in qla82xx_md_rw_32()948 rval = RD_REG_DWORD(off_value + CRB_INDIRECT_2M + in qla82xx_md_rw_32()2064 if (RD_REG_DWORD(®->host_int)) { in qla82xx_intr_handler()2065 stat = RD_REG_DWORD(®->host_status); in qla82xx_intr_handler()2130 host_int = RD_REG_DWORD(®->host_int); in qla82xx_msix_default()2134 stat = RD_REG_DWORD(®->host_status); in qla82xx_msix_default()2191 host_int = RD_REG_DWORD(®->host_int); in qla82xx_msix_rsp_q()2226 host_int = RD_REG_DWORD(®->host_int); in qla82xx_poll()[all …]
182 stat = RD_REG_DWORD(®->u.isp2300.host_status); in qla2300_intr_handler()3066 RD_REG_DWORD(®->iobase_addr); in qla2xxx_check_risc_status()3068 for (cnt = 10000; (RD_REG_DWORD(®->iobase_window) & BIT_0) == 0 && in qla2xxx_check_risc_status()3081 for (cnt = 100; (RD_REG_DWORD(®->iobase_window) & BIT_0) == 0 && in qla2xxx_check_risc_status()3093 if (RD_REG_DWORD(®->iobase_c8) & BIT_3) in qla2xxx_check_risc_status()3099 RD_REG_DWORD(®->iobase_window); in qla2xxx_check_risc_status()3142 stat = RD_REG_DWORD(®->host_status); in qla24xx_intr_handler()3149 hccr = RD_REG_DWORD(®->hccr); in qla24xx_intr_handler()3273 stat = RD_REG_DWORD(®->host_status); in qla24xx_msix_default()3280 hccr = RD_REG_DWORD(®->hccr); in qla24xx_msix_default()
2405 ha->pci_attr = RD_REG_DWORD(®->ctrl_status); in qla24xx_pci_config()2661 if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) in qla24xx_reset_risc()2667 if (!(RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE)) in qla24xx_reset_risc()2672 RD_REG_DWORD(®->hccr), in qla24xx_reset_risc()2673 RD_REG_DWORD(®->ctrl_status), in qla24xx_reset_risc()2674 (RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE)); in qla24xx_reset_risc()2698 RD_REG_DWORD(®->hccr), in qla24xx_reset_risc()2699 RD_REG_DWORD(®->mailbox0)); in qla24xx_reset_risc()2702 RD_REG_DWORD(®->ctrl_status); in qla24xx_reset_risc()2705 if ((RD_REG_DWORD(®->ctrl_status) & in qla24xx_reset_risc()[all …]
255 if (RD_REG_DWORD(®->isp82.hint) & in qla2x00_mailbox_command()301 if (RD_REG_DWORD(®->isp82.hint) & in qla2x00_mailbox_command()409 ictrl = RD_REG_DWORD(®->isp24.ictrl); in qla2x00_mailbox_command()410 host_status = RD_REG_DWORD(®->isp24.host_status); in qla2x00_mailbox_command()411 hccr = RD_REG_DWORD(®->isp24.hccr); in qla2x00_mailbox_command()560 RD_REG_DWORD(®->isp24.host_status), in qla2x00_mailbox_command()561 RD_REG_DWORD(®->isp24.ictrl), in qla2x00_mailbox_command()562 RD_REG_DWORD(®->isp24.istatus)); in qla2x00_mailbox_command()5193 stat = RD_REG_DWORD(®->host_status); in qla81xx_write_mpi_register()5204 RD_REG_DWORD(®->hccr); in qla81xx_write_mpi_register()
2143 cnt = RD_REG_DWORD(®->isp25mq.req_q_out); in __qla2x00_alloc_iocbs()2145 cnt = RD_REG_DWORD(®->isp82.req_q_out); in __qla2x00_alloc_iocbs()2147 cnt = RD_REG_DWORD(®->isp24.req_q_out); in __qla2x00_alloc_iocbs()2149 cnt = RD_REG_DWORD(®->ispfx00.req_q_out); in __qla2x00_alloc_iocbs()3283 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { in qla82xx_start_scsi()
1244 return ((RD_REG_DWORD(®82->host_int)) == ISP_REG_DISCONNECT); in qla2x00_isp_reg_stat()1246 return ((RD_REG_DWORD(®->host_status)) == in qla2x00_isp_reg_stat()1913 RD_REG_DWORD(®->ictrl); in qla24xx_enable_intrs()1928 RD_REG_DWORD(®->ictrl); in qla24xx_disable_intrs()6627 stat = RD_REG_DWORD(®->hccr); in qla2xxx_pci_mmio_enabled()6631 stat = RD_REG_DWORD(®->u.isp2300.host_status); in qla2xxx_pci_mmio_enabled()6635 stat = RD_REG_DWORD(®24->host_status); in qla2xxx_pci_mmio_enabled()
167 value = RD_REG_DWORD(window); in qla27xx_read32()
3950 if (RD_REG_DWORD(®->host_int)) { in qla8044_intr_handler()3951 stat = RD_REG_DWORD(®->host_status); in qla8044_intr_handler()
115 #define RD_REG_DWORD(addr) readl(addr) macro
6718 RD_REG_DWORD(ISP_ATIO_Q_OUT(vha)); in qlt_24xx_config_rings()
