2405 	ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);  in qla24xx_pci_config()
2661 		if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)  in qla24xx_reset_risc()
2667 	if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))  in qla24xx_reset_risc()
2672 	    RD_REG_DWORD(&reg->hccr),  in qla24xx_reset_risc()
2673 	    RD_REG_DWORD(&reg->ctrl_status),  in qla24xx_reset_risc()
2674 	    (RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE));  in qla24xx_reset_risc()
2698 	    RD_REG_DWORD(&reg->hccr),  in qla24xx_reset_risc()
2699 	    RD_REG_DWORD(&reg->mailbox0));  in qla24xx_reset_risc()
2702 	RD_REG_DWORD(&reg->ctrl_status);  in qla24xx_reset_risc()
2705 		if ((RD_REG_DWORD(&reg->ctrl_status) &  in qla24xx_reset_risc()
2711 	if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))  in qla24xx_reset_risc()
2716 	    RD_REG_DWORD(&reg->hccr),  in qla24xx_reset_risc()
2717 	    RD_REG_DWORD(&reg->ctrl_status));  in qla24xx_reset_risc()
2737 	RD_REG_DWORD(&reg->hccr);  in qla24xx_reset_risc()
2740 	RD_REG_DWORD(&reg->hccr);  in qla24xx_reset_risc()
2743 	RD_REG_DWORD(&reg->hccr);  in qla24xx_reset_risc()
2759 	    RD_REG_DWORD(&reg->hccr),  in qla24xx_reset_risc()
2780 	*data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);  in qla25xx_read_risc_sema_reg()
3912 	RD_REG_DWORD(&ioreg->hccr);  in qla24xx_config_rings()
6871 	RD_REG_DWORD(&reg->hccr);  in qla24xx_reset_adapter()
6873 	RD_REG_DWORD(&reg->hccr);  in qla24xx_reset_adapter()