Home
last modified time | relevance | path

Searched refs:PIPE_A (Results 1 – 25 of 25) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/i915/gvt/
Dhandlers.c755 [PIPE_A] = PRIMARY_A_FLIP_DONE, in pri_surf_mmio_write()
776 [PIPE_A] = SPRITE_A_FLIP_DONE, in spr_surf_mmio_write()
1912 MMIO_D(PIPEDSL(PIPE_A), D_ALL); in init_generic_mmio_info()
1917 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
1922 MMIO_D(PIPESTAT(PIPE_A), D_ALL); in init_generic_mmio_info()
1927 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); in init_generic_mmio_info()
1932 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); in init_generic_mmio_info()
1937 MMIO_D(CURCNTR(PIPE_A), D_ALL); in init_generic_mmio_info()
1941 MMIO_D(CURPOS(PIPE_A), D_ALL); in init_generic_mmio_info()
1945 MMIO_D(CURBASE(PIPE_A), D_ALL); in init_generic_mmio_info()
[all …]
Ddisplay.c46 pipe = PIPE_A; in get_edp_pipe()
74 if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES)) in pipe_is_enabled()
303 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; in emulate_monitor_status_change()
392 [PIPE_A] = PIPE_A_VBLANK, in emulate_vblank_on_pipe()
398 if (pipe < PIPE_A || pipe > PIPE_C) in emulate_vblank_on_pipe()
Dcmd_parser.c1174 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE}, in gen8_decode_mi_display_flip()
1176 [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE}, in gen8_decode_mi_display_flip()
1229 info->pipe = PIPE_A; in skl_decode_mi_display_flip()
1242 info->pipe = PIPE_A; in skl_decode_mi_display_flip()
Dinterrupt.c449 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_a, GEN8_DE_PIPE_ISR(PIPE_A));
/Linux-v4.19/drivers/gpu/drm/i915/
Dintel_pipe_crc.c172 case PIPE_A: in vlv_pipe_crc_ctl_reg()
254 if (pipe == PIPE_A) in i9xx_pipe_crc_ctl_reg()
271 case PIPE_A: in vlv_undo_pipe_scramble_reset()
294 if (pipe == PIPE_A) in g4x_undo_pipe_scramble_reset()
336 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A); in hsw_pipe_A_crc_wa()
410 IS_BROADWELL(dev_priv)) && pipe == PIPE_A) in ivb_pipe_crc_ctl_reg()
506 IS_BROADWELL(dev_priv)) && crtc->index == PIPE_A) in intel_crtc_set_crc_source()
Dintel_ddi.c1127 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | in hsw_fdi_link_train()
1135 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
1136 POSTING_READ(FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
1141 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
1171 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); in hsw_fdi_link_train()
1175 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
1176 POSTING_READ(FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
1182 temp = I915_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
1184 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); in hsw_fdi_link_train()
1185 POSTING_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
[all …]
Dintel_device_info.c748 info->num_scalers[PIPE_A] = 2; in intel_device_info_runtime_init()
768 info->num_sprites[PIPE_A] = 2; in intel_device_info_runtime_init()
814 disabled_mask |= BIT(PIPE_A); in intel_device_info_runtime_init()
823 case BIT(PIPE_A): in intel_device_info_runtime_init()
825 case BIT(PIPE_A) | BIT(PIPE_B): in intel_device_info_runtime_init()
826 case BIT(PIPE_A) | BIT(PIPE_C): in intel_device_info_runtime_init()
Dintel_crt.c226 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in hsw_disable_crt()
246 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in hsw_post_disable_crt()
257 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in hsw_pre_pll_enable_crt()
292 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in hsw_enable_crt()
1048 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; in intel_crt_init()
Dintel_fifo_underrun.c130 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : in ironlake_set_fifo_underrun_reporting()
196 uint32_t bit = (pch_transcoder == PIPE_A) ? in ibx_set_fifo_underrun_reporting()
Dintel_runtime_pm.c840 if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
841 i830_enable_pipe(dev_priv, PIPE_A); in i830_pipes_power_well_enable()
850 i830_disable_pipe(dev_priv, PIPE_A); in i830_pipes_power_well_disable()
856 return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE && in i830_pipes_power_well_enabled()
997 if (pipe != PIPE_A) in vlv_display_power_well_init()
1246 pipe = PIPE_A; in chv_dpio_cmn_power_well_enable()
1309 assert_pll_disabled(dev_priv, PIPE_A); in chv_dpio_cmn_power_well_disable()
1333 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; in assert_chv_phy_powergate()
1456 enum pipe pipe = PIPE_A; in chv_pipe_power_well_enabled()
1486 enum pipe pipe = PIPE_A; in chv_set_pipe_power_well()
[all …]
Dintel_pm.c483 case PIPE_A: in vlv_get_fifo_size()
941 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); in g4x_write_wm_values()
947 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in g4x_write_wm_values()
948 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); in g4x_write_wm_values()
991 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); in vlv_write_wm_values()
993 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) | in vlv_write_wm_values()
994 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in vlv_write_wm_values()
995 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); in vlv_write_wm_values()
1017 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) | in vlv_write_wm_values()
1018 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) | in vlv_write_wm_values()
[all …]
Dintel_dp.c597 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); in vlv_find_free_pps()
651 pipe = PIPE_A; in vlv_power_sequencer_pipe()
726 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe()
2653 *pipe = PIPE_A; in cpt_dp_port_selected()
3054 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
3667 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_dp_link_down()
3668 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_dp_link_down()
3672 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) | in intel_dp_link_down()
3681 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); in intel_dp_link_down()
3682 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_dp_link_down()
[all …]
Dintel_hdmi.c1418 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_hdmi()
1419 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_hdmi()
1422 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); in intel_disable_hdmi()
1436 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); in intel_disable_hdmi()
1437 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_hdmi()
1438 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_hdmi()
Dintel_display.c1471 if (pipe != PIPE_A) { in chv_enable_pll()
1578 I915_WRITE(DPLL(PIPE_A), in i9xx_disable_pll()
1579 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); in i9xx_disable_pll()
1602 if (pipe != PIPE_A) in vlv_disable_pll()
1619 if (pipe != PIPE_A) in chv_disable_pll()
1733 assert_fdi_rx_enabled(dev_priv, PIPE_A); in lpt_enable_pch_transcoder()
1736 val = I915_READ(TRANS_CHICKEN2(PIPE_A)); in lpt_enable_pch_transcoder()
1738 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); in lpt_enable_pch_transcoder()
1804 val = I915_READ(TRANS_CHICKEN2(PIPE_A)); in lpt_disable_pch_transcoder()
1806 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); in lpt_disable_pch_transcoder()
[all …]
Dintel_display.h31 PIPE_A = 0, enumerator
Dintel_sdvo.c1561 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_sdvo()
1562 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_sdvo()
1565 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); in intel_disable_sdvo()
1571 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); in intel_disable_sdvo()
1572 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_sdvo()
1573 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_sdvo()
Di915_irq.c763 i915_enable_pipestat(dev_priv, PIPE_A, in i915_enable_asle_pipestat()
1905 case PIPE_A: in i9xx_pipestat_irq_ack()
2342 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); in ibx_irq_handler()
3515 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in vlv_display_irq_postinstall()
4355 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
4533 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
4655 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in i965_irq_postinstall()
4656 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
Dvlv_dsi.c1077 *pipe = port == PORT_A ? PIPE_A : PIPE_B; in intel_dsi_get_hw_state()
1791 intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); in vlv_dsi_init()
1793 intel_encoder->crtc_mask = BIT(PIPE_A); in vlv_dsi_init()
Di915_trace.h88 __entry->frame[PIPE_A], __entry->scanline[PIPE_A],
Dintel_panel.c499 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in _vlv_get_backlight()
1631 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_setup_backlight()
Di915_cmd_parser.c616 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_A)),
Dintel_drv.h1223 case PIPE_A: in vlv_pipe_to_channel()
Di915_reg.h5650 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
6101 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
8020 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
/Linux-v4.19/drivers/video/fbdev/intelfb/
Dintelfbhw.c482 if (unlikely(pipe == PIPE_A)) in intelfbhw_active_pipe()
483 return PIPE_A; in intelfbhw_active_pipe()
488 if (likely(pipe == PIPE_A)) in intelfbhw_active_pipe()
489 return PIPE_A; in intelfbhw_active_pipe()
494 pipe = PIPE_A; in intelfbhw_active_pipe()
503 u32 palette_reg = (dinfo->pipe == PIPE_A) ? in intelfbhw_setcolreg()
Dintelfbhw.h182 #define PIPE_A 0 macro