Searched refs:PIPECONF (Results 1 – 8 of 8) sorted by relevance
| /Linux-v4.19/drivers/gpu/drm/i915/gvt/ |
| D | display.c | 62 if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE)) in edp_pipe_is_enabled()
77 if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE) in pipe_is_enabled()
303 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; in emulate_monitor_status_change()
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| D | handlers.c | 1917 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
1918 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
1919 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
1920 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
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| /Linux-v4.19/drivers/gpu/drm/i915/ |
| D | intel_display.c | 1092 i915_reg_t reg = PIPECONF(cpu_transcoder); in intel_wait_for_pipe_off()
1272 u32 val = I915_READ(PIPECONF(cpu_transcoder)); in assert_pipe()
1694 pipeconf_val = I915_READ(PIPECONF(pipe)); in ironlake_enable_pch_transcoder()
1741 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); in lpt_enable_pch_transcoder()
1853 reg = PIPECONF(cpu_transcoder); in intel_enable_pipe()
1892 reg = PIPECONF(cpu_transcoder); in intel_disable_pipe()
4273 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_pll_enable()
4345 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_disable()
4373 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_disable()
4698 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; in ironlake_pch_enable()
[all …]
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| D | intel_runtime_pm.c | 840 if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
842 if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
856 return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE && in i830_pipes_power_well_enabled()
857 I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in i830_pipes_power_well_enabled()
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| D | intel_crt.c | 650 pipeconf_reg = PIPECONF(pipe); in intel_crt_load_detect()
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| D | vlv_dsi.c | 1053 enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in intel_dsi_get_hw_state()
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| D | intel_dp.c | 5725 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); in intel_dp_set_drrs_state()
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| D | i915_reg.h | 5653 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) macro
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