1092 		i915_reg_t reg = PIPECONF(cpu_transcoder);  in intel_wait_for_pipe_off()
1272 		u32 val = I915_READ(PIPECONF(cpu_transcoder));  in assert_pipe()
1694 	pipeconf_val = I915_READ(PIPECONF(pipe));  in ironlake_enable_pch_transcoder()
1741 	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));  in lpt_enable_pch_transcoder()
1853 	reg = PIPECONF(cpu_transcoder);  in intel_enable_pipe()
1892 	reg = PIPECONF(cpu_transcoder);  in intel_disable_pipe()
4273 	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;  in ironlake_fdi_pll_enable()
4345 	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;  in ironlake_fdi_disable()
4373 	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;  in ironlake_fdi_disable()
4698 		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;  in ironlake_pch_enable()
7373 	if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {  in intel_get_pipe_timings()
7427 		pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;  in i9xx_set_pipeconf()
7469 	I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);  in i9xx_set_pipeconf()
7470 	POSTING_READ(PIPECONF(intel_crtc->pipe));  in i9xx_set_pipeconf()
7843 	tmp = I915_READ(PIPECONF(crtc->pipe));  in i9xx_get_pipe_config()
8407 	I915_WRITE(PIPECONF(pipe), val);  in ironlake_set_pipeconf()
8408 	POSTING_READ(PIPECONF(pipe));  in ironlake_set_pipeconf()
8426 	I915_WRITE(PIPECONF(cpu_transcoder), val);  in haswell_set_pipeconf()
8427 	POSTING_READ(PIPECONF(cpu_transcoder));  in haswell_set_pipeconf()
8892 	tmp = I915_READ(PIPECONF(crtc->pipe));  in ironlake_get_pipe_config()
9389 	tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));  in hsw_get_transcoder_state()
15340 	I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);  in i830_enable_pipe()
15341 	POSTING_READ(PIPECONF(pipe));  in i830_enable_pipe()
15359 	I915_WRITE(PIPECONF(pipe), 0);  in i830_disable_pipe()
15360 	POSTING_READ(PIPECONF(pipe));  in i830_disable_pipe()
15438 		i915_reg_t reg = PIPECONF(cpu_transcoder);  in intel_sanitize_crtc()
16129 		error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));  in intel_display_capture_error_state()