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Searched refs:OUT_RING (Results 1 – 25 of 29) sorted by relevance

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/Linux-v4.19/drivers/gpu/drm/nouveau/
Dnvc0_fbcon.c44 OUT_RING (chan, 1); in nvc0_fbcon_fillrect()
49 OUT_RING (chan, ((uint32_t *)info->pseudo_palette)[rect->color]); in nvc0_fbcon_fillrect()
51 OUT_RING (chan, rect->color); in nvc0_fbcon_fillrect()
53 OUT_RING (chan, rect->dx); in nvc0_fbcon_fillrect()
54 OUT_RING (chan, rect->dy); in nvc0_fbcon_fillrect()
55 OUT_RING (chan, rect->dx + rect->width); in nvc0_fbcon_fillrect()
56 OUT_RING (chan, rect->dy + rect->height); in nvc0_fbcon_fillrect()
59 OUT_RING (chan, 3); in nvc0_fbcon_fillrect()
78 OUT_RING (chan, 0); in nvc0_fbcon_copyarea()
80 OUT_RING (chan, region->dx); in nvc0_fbcon_copyarea()
[all …]
Dnv50_fbcon.c44 OUT_RING(chan, 1); in nv50_fbcon_fillrect()
49 OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]); in nv50_fbcon_fillrect()
51 OUT_RING(chan, rect->color); in nv50_fbcon_fillrect()
53 OUT_RING(chan, rect->dx); in nv50_fbcon_fillrect()
54 OUT_RING(chan, rect->dy); in nv50_fbcon_fillrect()
55 OUT_RING(chan, rect->dx + rect->width); in nv50_fbcon_fillrect()
56 OUT_RING(chan, rect->dy + rect->height); in nv50_fbcon_fillrect()
59 OUT_RING(chan, 3); in nv50_fbcon_fillrect()
78 OUT_RING(chan, 0); in nv50_fbcon_copyarea()
80 OUT_RING(chan, region->dx); in nv50_fbcon_copyarea()
[all …]
Dnv04_fbcon.c42 OUT_RING(chan, (region->sy << 16) | region->sx); in nv04_fbcon_copyarea()
43 OUT_RING(chan, (region->dy << 16) | region->dx); in nv04_fbcon_copyarea()
44 OUT_RING(chan, (region->height << 16) | region->width); in nv04_fbcon_copyarea()
62 OUT_RING(chan, (rect->rop != ROP_COPY) ? 1 : 3); in nv04_fbcon_fillrect()
66 OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]); in nv04_fbcon_fillrect()
68 OUT_RING(chan, rect->color); in nv04_fbcon_fillrect()
70 OUT_RING(chan, (rect->dx << 16) | rect->dy); in nv04_fbcon_fillrect()
71 OUT_RING(chan, (rect->width << 16) | rect->height); in nv04_fbcon_fillrect()
105 OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff)); in nv04_fbcon_imageblit()
106 OUT_RING(chan, ((image->dy + image->height) << 16) | in nv04_fbcon_imageblit()
[all …]
Dnvc0_fence.c37 OUT_RING (chan, upper_32_bits(virtual)); in nvc0_fence_emit32()
38 OUT_RING (chan, lower_32_bits(virtual)); in nvc0_fence_emit32()
39 OUT_RING (chan, sequence); in nvc0_fence_emit32()
40 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); in nvc0_fence_emit32()
41 OUT_RING (chan, 0x00000000); in nvc0_fence_emit32()
53 OUT_RING (chan, upper_32_bits(virtual)); in nvc0_fence_sync32()
54 OUT_RING (chan, lower_32_bits(virtual)); in nvc0_fence_sync32()
55 OUT_RING (chan, sequence); in nvc0_fence_sync32()
56 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL | in nvc0_fence_sync32()
Dnouveau_bo.c714 OUT_RING (chan, handle & 0x0000ffff); in nve0_bo_move_init()
728 OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); in nve0_bo_move_copy()
729 OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); in nve0_bo_move_copy()
730 OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); in nve0_bo_move_copy()
731 OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); in nve0_bo_move_copy()
732 OUT_RING (chan, PAGE_SIZE); in nve0_bo_move_copy()
733 OUT_RING (chan, PAGE_SIZE); in nve0_bo_move_copy()
734 OUT_RING (chan, PAGE_SIZE); in nve0_bo_move_copy()
735 OUT_RING (chan, new_reg->num_pages); in nve0_bo_move_copy()
747 OUT_RING (chan, handle); in nvc0_bo_move_init()
[all …]
Dnv17_fence.c54 OUT_RING (prev, fctx->sema.handle); in nv17_fence_sync()
55 OUT_RING (prev, 0); in nv17_fence_sync()
56 OUT_RING (prev, value + 0); in nv17_fence_sync()
57 OUT_RING (prev, value + 1); in nv17_fence_sync()
63 OUT_RING (chan, fctx->sema.handle); in nv17_fence_sync()
64 OUT_RING (chan, 0); in nv17_fence_sync()
65 OUT_RING (chan, value + 1); in nv17_fence_sync()
66 OUT_RING (chan, value + 2); in nv17_fence_sync()
Dnv84_fence.c38 OUT_RING (chan, chan->vram.handle); in nv84_fence_emit32()
40 OUT_RING (chan, upper_32_bits(virtual)); in nv84_fence_emit32()
41 OUT_RING (chan, lower_32_bits(virtual)); in nv84_fence_emit32()
42 OUT_RING (chan, sequence); in nv84_fence_emit32()
43 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); in nv84_fence_emit32()
44 OUT_RING (chan, 0x00000000); in nv84_fence_emit32()
56 OUT_RING (chan, chan->vram.handle); in nv84_fence_sync32()
58 OUT_RING (chan, upper_32_bits(virtual)); in nv84_fence_sync32()
59 OUT_RING (chan, lower_32_bits(virtual)); in nv84_fence_sync32()
60 OUT_RING (chan, sequence); in nv84_fence_sync32()
[all …]
Dnouveau_dma.h100 OUT_RING(struct nouveau_channel *chan, int data) in OUT_RING() function
111 OUT_RING(chan, 0x00000000 | (subc << 13) | (size << 18) | mthd); in BEGIN_NV04()
117 OUT_RING(chan, 0x40000000 | (subc << 13) | (size << 18) | mthd); in BEGIN_NI04()
123 OUT_RING(chan, 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2)); in BEGIN_NVC0()
129 OUT_RING(chan, 0x60000000 | (size << 16) | (subc << 13) | (mthd >> 2)); in BEGIN_NIC0()
135 OUT_RING(chan, 0x80000000 | (data << 16) | (subc << 13) | (mthd >> 2)); in BEGIN_IMC0()
Dnv04_fence.c46 OUT_RING (chan, fence->base.seqno); in nv04_fence_emit()
Dnv10_fence.c36 OUT_RING (chan, fence->base.seqno); in nv10_fence_emit()
Dnouveau_display.c771 OUT_RING (chan, 0x00000000); in nouveau_page_flip_emit()
854 OUT_RING (chan, 0); in nouveau_crtc_page_flip()
856 OUT_RING (chan, head); in nouveau_crtc_page_flip()
858 OUT_RING (chan, 0); in nouveau_crtc_page_flip()
860 OUT_RING (chan, 0); in nouveau_crtc_page_flip()
Dnouveau_gem.c796 OUT_RING(chan, (nvbo->bo.offset + push[i].offset) | 2); in nouveau_gem_ioctl_pushbuf()
797 OUT_RING(chan, 0); in nouveau_gem_ioctl_pushbuf()
830 OUT_RING(chan, 0x20000000 | in nouveau_gem_ioctl_pushbuf()
832 OUT_RING(chan, 0); in nouveau_gem_ioctl_pushbuf()
834 OUT_RING(chan, 0); in nouveau_gem_ioctl_pushbuf()
/Linux-v4.19/drivers/gpu/drm/r128/
Dr128_state.c49 OUT_RING(CCE_PACKET0(R128_AUX1_SC_LEFT, 3)); in r128_emit_clip_rects()
50 OUT_RING(boxes[0].x1); in r128_emit_clip_rects()
51 OUT_RING(boxes[0].x2 - 1); in r128_emit_clip_rects()
52 OUT_RING(boxes[0].y1); in r128_emit_clip_rects()
53 OUT_RING(boxes[0].y2 - 1); in r128_emit_clip_rects()
58 OUT_RING(CCE_PACKET0(R128_AUX2_SC_LEFT, 3)); in r128_emit_clip_rects()
59 OUT_RING(boxes[1].x1); in r128_emit_clip_rects()
60 OUT_RING(boxes[1].x2 - 1); in r128_emit_clip_rects()
61 OUT_RING(boxes[1].y1); in r128_emit_clip_rects()
62 OUT_RING(boxes[1].y2 - 1); in r128_emit_clip_rects()
[all …]
Dr128_drv.h470 OUT_RING(CCE_PACKET0(R128_WAIT_UNTIL, 0)); \
471 OUT_RING(R128_EVENT_CRTC_OFFSET); \
529 #define OUT_RING(x) do { \ macro
/Linux-v4.19/drivers/gpu/drm/i810/
Di810_dma.c463 OUT_RING(GFX_OP_COLOR_FACTOR); in i810EmitContextVerified()
464 OUT_RING(code[I810_CTXREG_CF1]); in i810EmitContextVerified()
466 OUT_RING(GFX_OP_STIPPLE); in i810EmitContextVerified()
467 OUT_RING(code[I810_CTXREG_ST1]); in i810EmitContextVerified()
474 OUT_RING(tmp); in i810EmitContextVerified()
481 OUT_RING(0); in i810EmitContextVerified()
495 OUT_RING(GFX_OP_MAP_INFO); in i810EmitTexVerified()
496 OUT_RING(code[I810_TEXREG_MI1]); in i810EmitTexVerified()
497 OUT_RING(code[I810_TEXREG_MI2]); in i810EmitTexVerified()
498 OUT_RING(code[I810_TEXREG_MI3]); in i810EmitTexVerified()
[all …]
Di810_drv.h164 #define OUT_RING(n) do { \ macro
/Linux-v4.19/drivers/gpu/drm/msm/adreno/
Da5xx_gpu.c185 OUT_RING(ring, ptr[i]); in a5xx_submit_in_rb()
222 OUT_RING(ring, 0x02); in a5xx_submit()
226 OUT_RING(ring, 0); in a5xx_submit()
230 OUT_RING(ring, lower_32_bits(a5xx_gpu->preempt_iova[submit->ring->id])); in a5xx_submit()
231 OUT_RING(ring, upper_32_bits(a5xx_gpu->preempt_iova[submit->ring->id])); in a5xx_submit()
235 OUT_RING(ring, 1); in a5xx_submit()
239 OUT_RING(ring, 0x02); in a5xx_submit()
243 OUT_RING(ring, 0x02); in a5xx_submit()
255 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); in a5xx_submit()
256 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova)); in a5xx_submit()
[all …]
Da3xx_gpu.c51 OUT_RING(ring, 0x000003f7); in a3xx_me_init()
52 OUT_RING(ring, 0x00000000); in a3xx_me_init()
53 OUT_RING(ring, 0x00000000); in a3xx_me_init()
54 OUT_RING(ring, 0x00000000); in a3xx_me_init()
55 OUT_RING(ring, 0x00000080); in a3xx_me_init()
56 OUT_RING(ring, 0x00000100); in a3xx_me_init()
57 OUT_RING(ring, 0x00000180); in a3xx_me_init()
58 OUT_RING(ring, 0x00006600); in a3xx_me_init()
59 OUT_RING(ring, 0x00000150); in a3xx_me_init()
60 OUT_RING(ring, 0x0000014e); in a3xx_me_init()
[all …]
Da4xx_gpu.c123 OUT_RING(ring, 0x000003f7); in a4xx_me_init()
124 OUT_RING(ring, 0x00000000); in a4xx_me_init()
125 OUT_RING(ring, 0x00000000); in a4xx_me_init()
126 OUT_RING(ring, 0x00000000); in a4xx_me_init()
127 OUT_RING(ring, 0x00000080); in a4xx_me_init()
128 OUT_RING(ring, 0x00000100); in a4xx_me_init()
129 OUT_RING(ring, 0x00000180); in a4xx_me_init()
130 OUT_RING(ring, 0x00006600); in a4xx_me_init()
131 OUT_RING(ring, 0x00000150); in a4xx_me_init()
132 OUT_RING(ring, 0x0000014e); in a4xx_me_init()
[all …]
Da6xx_gpu.c77 OUT_RING(ring, PC_CCU_INVALIDATE_DEPTH); in a6xx_submit()
80 OUT_RING(ring, PC_CCU_INVALIDATE_COLOR); in a6xx_submit()
92 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); in a6xx_submit()
93 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova)); in a6xx_submit()
94 OUT_RING(ring, submit->cmd[i].size); in a6xx_submit()
101 OUT_RING(ring, submit->seqno); in a6xx_submit()
108 OUT_RING(ring, CACHE_FLUSH_TS | (1 << 31)); in a6xx_submit()
109 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence))); in a6xx_submit()
110 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); in a6xx_submit()
111 OUT_RING(ring, submit->seqno); in a6xx_submit()
[all …]
Da5xx_power.c189 OUT_RING(ring, 0); in a5xx_gpmu_init()
193 OUT_RING(ring, lower_32_bits(a5xx_gpu->gpmu_iova)); in a5xx_gpmu_init()
194 OUT_RING(ring, upper_32_bits(a5xx_gpu->gpmu_iova)); in a5xx_gpmu_init()
195 OUT_RING(ring, a5xx_gpu->gpmu_dwords); in a5xx_gpmu_init()
199 OUT_RING(ring, 1); in a5xx_gpmu_init()
Dadreno_gpu.h246 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF)); in OUT_PKT0()
254 OUT_RING(ring, CP_TYPE2_PKT); in OUT_PKT2()
261 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8)); in OUT_PKT3()
283 OUT_RING(ring, PKT4(regindx, cnt)); in OUT_PKT4()
290 OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) | in OUT_PKT7()
Dadreno_gpu.c305 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); in adreno_submit()
306 OUT_RING(ring, submit->cmd[i].size); in adreno_submit()
313 OUT_RING(ring, submit->seqno); in adreno_submit()
321 OUT_RING(ring, HLSQ_FLUSH); in adreno_submit()
324 OUT_RING(ring, 0x00000000); in adreno_submit()
329 OUT_RING(ring, CACHE_FLUSH_TS | BIT(31)); in adreno_submit()
330 OUT_RING(ring, rbmemptr(ring, fence)); in adreno_submit()
331 OUT_RING(ring, submit->seqno); in adreno_submit()
337 OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG)); in adreno_submit()
338 OUT_RING(ring, 0x00000000); in adreno_submit()
/Linux-v4.19/drivers/video/fbdev/intelfb/
Dintelfbhw.c1549 OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE); in do_flush()
1550 OUT_RING(MI_NOOP); in do_flush()
1687 OUT_RING(br00); in intelfbhw_do_fillrect()
1688 OUT_RING(br13); in intelfbhw_do_fillrect()
1689 OUT_RING(br14); in intelfbhw_do_fillrect()
1690 OUT_RING(br09); in intelfbhw_do_fillrect()
1691 OUT_RING(br16); in intelfbhw_do_fillrect()
1692 OUT_RING(MI_NOOP); in intelfbhw_do_fillrect()
1736 OUT_RING(br00); in intelfbhw_do_bitblt()
1737 OUT_RING(br13); in intelfbhw_do_bitblt()
[all …]
/Linux-v4.19/drivers/gpu/drm/msm/
Dmsm_ringbuffer.h53 OUT_RING(struct msm_ringbuffer *ring, uint32_t data) in OUT_RING() function

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