463 	OUT_RING(GFX_OP_COLOR_FACTOR);  in i810EmitContextVerified()
464 	OUT_RING(code[I810_CTXREG_CF1]);  in i810EmitContextVerified()
466 	OUT_RING(GFX_OP_STIPPLE);  in i810EmitContextVerified()
467 	OUT_RING(code[I810_CTXREG_ST1]);  in i810EmitContextVerified()
474 			OUT_RING(tmp);  in i810EmitContextVerified()
481 		OUT_RING(0);  in i810EmitContextVerified()
495 	OUT_RING(GFX_OP_MAP_INFO);  in i810EmitTexVerified()
496 	OUT_RING(code[I810_TEXREG_MI1]);  in i810EmitTexVerified()
497 	OUT_RING(code[I810_TEXREG_MI2]);  in i810EmitTexVerified()
498 	OUT_RING(code[I810_TEXREG_MI3]);  in i810EmitTexVerified()
505 			OUT_RING(tmp);  in i810EmitTexVerified()
512 		OUT_RING(0);  in i810EmitTexVerified()
530 		OUT_RING(CMD_OP_DESTBUFFER_INFO);  in i810EmitDestVerified()
531 		OUT_RING(tmp);  in i810EmitDestVerified()
538 	OUT_RING(CMD_OP_Z_BUFFER_INFO);  in i810EmitDestVerified()
539 	OUT_RING(dev_priv->zi1);  in i810EmitDestVerified()
541 	OUT_RING(GFX_OP_DESTBUFFER_VARS);  in i810EmitDestVerified()
542 	OUT_RING(code[I810_DESTREG_DV1]);  in i810EmitDestVerified()
544 	OUT_RING(GFX_OP_DRAWRECT_INFO);  in i810EmitDestVerified()
545 	OUT_RING(code[I810_DESTREG_DR1]);  in i810EmitDestVerified()
546 	OUT_RING(code[I810_DESTREG_DR2]);  in i810EmitDestVerified()
547 	OUT_RING(code[I810_DESTREG_DR3]);  in i810EmitDestVerified()
548 	OUT_RING(code[I810_DESTREG_DR4]);  in i810EmitDestVerified()
549 	OUT_RING(0);  in i810EmitDestVerified()
627 			OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);  in i810_dma_dispatch_clear()
628 			OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);  in i810_dma_dispatch_clear()
629 			OUT_RING((height << 16) | width);  in i810_dma_dispatch_clear()
630 			OUT_RING(start);  in i810_dma_dispatch_clear()
631 			OUT_RING(clear_color);  in i810_dma_dispatch_clear()
632 			OUT_RING(0);  in i810_dma_dispatch_clear()
638 			OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);  in i810_dma_dispatch_clear()
639 			OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);  in i810_dma_dispatch_clear()
640 			OUT_RING((height << 16) | width);  in i810_dma_dispatch_clear()
641 			OUT_RING(dev_priv->back_offset + start);  in i810_dma_dispatch_clear()
642 			OUT_RING(clear_color);  in i810_dma_dispatch_clear()
643 			OUT_RING(0);  in i810_dma_dispatch_clear()
649 			OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);  in i810_dma_dispatch_clear()
650 			OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);  in i810_dma_dispatch_clear()
651 			OUT_RING((height << 16) | width);  in i810_dma_dispatch_clear()
652 			OUT_RING(dev_priv->depth_offset + start);  in i810_dma_dispatch_clear()
653 			OUT_RING(clear_zval);  in i810_dma_dispatch_clear()
654 			OUT_RING(0);  in i810_dma_dispatch_clear()
690 		OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4);  in i810_dma_dispatch_swap()
691 		OUT_RING(pitch | (0xCC << 16));  in i810_dma_dispatch_swap()
692 		OUT_RING((h << 16) | (w * cpp));  in i810_dma_dispatch_swap()
694 			OUT_RING(dev_priv->front_offset + start);  in i810_dma_dispatch_swap()
696 			OUT_RING(dev_priv->back_offset + start);  in i810_dma_dispatch_swap()
697 		OUT_RING(pitch);  in i810_dma_dispatch_swap()
699 			OUT_RING(dev_priv->back_offset + start);  in i810_dma_dispatch_swap()
701 			OUT_RING(dev_priv->front_offset + start);  in i810_dma_dispatch_swap()
748 				OUT_RING(GFX_OP_SCISSOR | SC_UPDATE_SCISSOR |  in i810_dma_dispatch_vertex()
750 				OUT_RING(GFX_OP_SCISSOR_INFO);  in i810_dma_dispatch_vertex()
751 				OUT_RING(box[i].x1 | (box[i].y1 << 16));  in i810_dma_dispatch_vertex()
752 				OUT_RING((box[i].x2 -  in i810_dma_dispatch_vertex()
758 			OUT_RING(CMD_OP_BATCH_BUFFER);  in i810_dma_dispatch_vertex()
759 			OUT_RING(start | BB1_PROTECTED);  in i810_dma_dispatch_vertex()
760 			OUT_RING(start + used - 4);  in i810_dma_dispatch_vertex()
761 			OUT_RING(0);  in i810_dma_dispatch_vertex()
774 		OUT_RING(CMD_STORE_DWORD_IDX);  in i810_dma_dispatch_vertex()
775 		OUT_RING(20);  in i810_dma_dispatch_vertex()
776 		OUT_RING(dev_priv->counter);  in i810_dma_dispatch_vertex()
777 		OUT_RING(CMD_STORE_DWORD_IDX);  in i810_dma_dispatch_vertex()
778 		OUT_RING(buf_priv->my_use_idx);  in i810_dma_dispatch_vertex()
779 		OUT_RING(I810_BUF_FREE);  in i810_dma_dispatch_vertex()
780 		OUT_RING(CMD_REPORT_HEAD);  in i810_dma_dispatch_vertex()
781 		OUT_RING(0);  in i810_dma_dispatch_vertex()
799 	OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);  in i810_dma_dispatch_flip()
800 	OUT_RING(0);  in i810_dma_dispatch_flip()
808 	OUT_RING(CMD_OP_FRONTBUFFER_INFO | (pitch << 5) /*| ASYNC_FLIP */ );  in i810_dma_dispatch_flip()
810 		OUT_RING(dev_priv->back_offset);  in i810_dma_dispatch_flip()
813 		OUT_RING(dev_priv->front_offset);  in i810_dma_dispatch_flip()
816 	OUT_RING(0);  in i810_dma_dispatch_flip()
820 	OUT_RING(CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP);  in i810_dma_dispatch_flip()
821 	OUT_RING(0);  in i810_dma_dispatch_flip()
840 	OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);  in i810_dma_quiescent()
841 	OUT_RING(CMD_REPORT_HEAD);  in i810_dma_quiescent()
842 	OUT_RING(0);  in i810_dma_quiescent()
843 	OUT_RING(0);  in i810_dma_quiescent()
859 	OUT_RING(CMD_REPORT_HEAD);  in i810_flush_queue()
860 	OUT_RING(0);  in i810_flush_queue()
1066 	OUT_RING(CMD_OP_BATCH_BUFFER);  in i810_dma_dispatch_mc()
1067 	OUT_RING(start | BB1_PROTECTED);  in i810_dma_dispatch_mc()
1068 	OUT_RING(start + used - 4);  in i810_dma_dispatch_mc()
1069 	OUT_RING(0);  in i810_dma_dispatch_mc()
1073 	OUT_RING(CMD_STORE_DWORD_IDX);  in i810_dma_dispatch_mc()
1074 	OUT_RING(buf_priv->my_use_idx);  in i810_dma_dispatch_mc()
1075 	OUT_RING(I810_BUF_FREE);  in i810_dma_dispatch_mc()
1076 	OUT_RING(0);  in i810_dma_dispatch_mc()
1078 	OUT_RING(CMD_STORE_DWORD_IDX);  in i810_dma_dispatch_mc()
1079 	OUT_RING(16);  in i810_dma_dispatch_mc()
1080 	OUT_RING(last_render);  in i810_dma_dispatch_mc()
1081 	OUT_RING(0);  in i810_dma_dispatch_mc()