Searched refs:MMC_TIMING_UHS_DDR50 (Results 1 – 25 of 25) sorted by relevance
62 #define MMC_TIMING_UHS_DDR50 7 macro556 card->host->ios.timing <= MMC_TIMING_UHS_DDR50; in mmc_card_uhs()
33 ios->timing == MMC_TIMING_UHS_DDR50) in dw_mci_hi3798cv200_set_ios()
280 case MMC_TIMING_UHS_DDR50: in pxav3_set_uhs_signaling()293 uhs == MMC_TIMING_UHS_DDR50) { in pxav3_set_uhs_signaling()
207 else if ((timing == MMC_TIMING_UHS_DDR50) || in xenon_set_uhs_signaling()342 if (host->timing == MMC_TIMING_UHS_DDR50 || in xenon_execute_tuning()
619 case MMC_TIMING_UHS_DDR50: in xenon_emmc_phy_set()749 case MMC_TIMING_UHS_DDR50: in xenon_hs_delay_adj()
995 case MMC_TIMING_UHS_DDR50: in sd_set_timing()1076 case MMC_TIMING_UHS_DDR50: in sdmmc_set_ios()1296 case MMC_TIMING_UHS_DDR50: in sdmmc_execute_tuning()1311 else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) in sdmmc_execute_tuning()
284 case MMC_TIMING_UHS_DDR50: in arasan_select_phy_clock()
300 case MMC_TIMING_UHS_DDR50: in sdhci_st_set_uhs_signaling()
676 if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52) in sdhci_omap_set_uhs_signaling()828 pinctrl_state[MMC_TIMING_UHS_DDR50] = state; in sdhci_omap_config_iodelay_pinctrl_state()
246 if (timing == MMC_TIMING_UHS_DDR50 || in tegra_sdhci_set_uhs_signaling()
748 if (ios->timing != MMC_TIMING_UHS_DDR50) { in usdhi6_clk_set()851 if (ios->timing == MMC_TIMING_UHS_DDR50) in usdhi6_set_ios()858 mode = ios->timing == MMC_TIMING_UHS_DDR50; in usdhi6_set_ios()
886 case MMC_TIMING_UHS_DDR50: in esdhc_change_pinstate()987 case MMC_TIMING_UHS_DDR50: in esdhc_set_uhs_signaling()
1077 case MMC_TIMING_UHS_DDR50: in sd_set_timing()1143 case MMC_TIMING_UHS_DDR50: in sdmmc_set_ios()
737 if (ios->timing != MMC_TIMING_UHS_DDR50 && in sunxi_mmc_clk_set_phase()881 if (ios->timing == MMC_TIMING_UHS_DDR50 || in sunxi_mmc_set_clk()
1380 case MMC_TIMING_UHS_DDR50: in sdhci_get_preset_value()1709 else if ((timing == MMC_TIMING_UHS_DDR50) || in sdhci_set_uhs_signaling()1784 ios->timing == MMC_TIMING_UHS_DDR50 || in sdhci_set_ios()1849 (ios->timing == MMC_TIMING_UHS_DDR50) || in sdhci_set_ios()2294 case MMC_TIMING_UHS_DDR50: in sdhci_execute_tuning()
353 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || in mmci_set_clkreg()826 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || in mmci_start_data()
315 if (ios.timing == MMC_TIMING_UHS_DDR50 || in msm_get_clock_rate_for_bus_mode()1166 case MMC_TIMING_UHS_DDR50: in sdhci_msm_set_uhs_signaling()
628 (ios->timing != MMC_TIMING_UHS_DDR50) && in omap_hsmmc_set_clock()649 ios->timing == MMC_TIMING_UHS_DDR50) in omap_hsmmc_set_bus_width()
382 ios->timing == MMC_TIMING_UHS_DDR50 || in meson_mmc_timing_is_ddr()
697 if (timing == MMC_TIMING_UHS_DDR50 || in msdc_set_mclk()
1452 ios->timing == MMC_TIMING_UHS_DDR50 || in dw_mci_set_ios()
143 case MMC_TIMING_UHS_DDR50: in mmc_ios_show()
452 timing = MMC_TIMING_UHS_DDR50; in sd_set_bus_speed_mode()624 card->host->ios.timing == MMC_TIMING_UHS_DDR50 || in mmc_sd_init_uhs_card()635 if (err && card->host->ios.timing == MMC_TIMING_UHS_DDR50) { in mmc_sd_init_uhs_card()
467 timing = MMC_TIMING_UHS_DDR50; in sdio_set_bus_speed_mode()
663 case MMC_TIMING_UHS_DDR50: in gb_mmc_set_ios()