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Searched refs:MHZ (Results 1 – 25 of 53) sorted by relevance

123

/Linux-v4.19/drivers/clk/samsung/
Dclk-s3c2410.c165 PLL_S3C2410_MPLL_RATE(12 * MHZ, 270000000, 127, 1, 1),
166 PLL_S3C2410_MPLL_RATE(12 * MHZ, 268000000, 126, 1, 1),
167 PLL_S3C2410_MPLL_RATE(12 * MHZ, 266000000, 125, 1, 1),
168 PLL_S3C2410_MPLL_RATE(12 * MHZ, 226000000, 105, 1, 1),
169 PLL_S3C2410_MPLL_RATE(12 * MHZ, 210000000, 132, 2, 1),
171 PLL_S3C2410_MPLL_RATE(12 * MHZ, 202800000, 161, 3, 1),
172 PLL_S3C2410_MPLL_RATE(12 * MHZ, 192000000, 88, 1, 1),
173 PLL_S3C2410_MPLL_RATE(12 * MHZ, 186000000, 85, 1, 1),
174 PLL_S3C2410_MPLL_RATE(12 * MHZ, 180000000, 82, 1, 1),
175 PLL_S3C2410_MPLL_RATE(12 * MHZ, 170000000, 77, 1, 1),
[all …]
Dclk-exynos3250.c673 PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
674 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
675 PLL_35XX_RATE(24 * MHZ, 1066000000, 533, 6, 1),
676 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
677 PLL_35XX_RATE(24 * MHZ, 960000000, 320, 4, 1),
678 PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
679 PLL_35XX_RATE(24 * MHZ, 850000000, 425, 6, 1),
680 PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
681 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
682 PLL_35XX_RATE(24 * MHZ, 667000000, 667, 12, 1),
[all …]
Dclk-exynos4.c1269 PLL_4508_RATE(24 * MHZ, 1200000000, 150, 3, 1, 28),
1270 PLL_4508_RATE(24 * MHZ, 1000000000, 250, 6, 1, 28),
1271 PLL_4508_RATE(24 * MHZ, 800000000, 200, 6, 1, 28),
1272 PLL_4508_RATE(24 * MHZ, 666857142, 389, 14, 1, 13),
1273 PLL_4508_RATE(24 * MHZ, 600000000, 100, 4, 1, 13),
1274 PLL_4508_RATE(24 * MHZ, 533000000, 533, 24, 1, 5),
1275 PLL_4508_RATE(24 * MHZ, 500000000, 250, 6, 2, 28),
1276 PLL_4508_RATE(24 * MHZ, 400000000, 200, 6, 2, 28),
1277 PLL_4508_RATE(24 * MHZ, 200000000, 200, 6, 3, 28),
1282 PLL_4600_RATE(24 * MHZ, 192000000, 48, 3, 1, 0, 0),
[all …]
Dclk-exynos5250.c728 PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0),
730 PLL_36XX_RATE(24 * MHZ, 70500000, 94, 2, 4, 0),
737 PLL_36XX_RATE(24 * MHZ, 192000000, 64, 2, 2, 0),
738 PLL_36XX_RATE(24 * MHZ, 180633605, 90, 3, 2, 20762),
739 PLL_36XX_RATE(24 * MHZ, 180000000, 90, 3, 2, 0),
740 PLL_36XX_RATE(24 * MHZ, 73728000, 98, 2, 4, 19923),
741 PLL_36XX_RATE(24 * MHZ, 67737602, 90, 2, 4, 20762),
742 PLL_36XX_RATE(24 * MHZ, 49152000, 98, 3, 4, 19923),
743 PLL_36XX_RATE(24 * MHZ, 45158401, 90, 3, 4, 20762),
744 PLL_36XX_RATE(24 * MHZ, 32768001, 131, 3, 5, 4719),
[all …]
Dclk-exynos5260.c26 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
27 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
28 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
29 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
30 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
31 PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
32 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
33 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
34 PLL_35XX_RATE(24 * MHZ, 933000000, 311, 4, 1),
35 PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
[all …]
Dclk-exynos5410.c229 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
230 PLL_36XX_RATE(24 * MHZ, 333000000U, 111, 2, 2, 0),
231 PLL_36XX_RATE(24 * MHZ, 300000000U, 100, 2, 2, 0),
232 PLL_36XX_RATE(24 * MHZ, 266000000U, 266, 3, 3, 0),
233 PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0),
234 PLL_36XX_RATE(24 * MHZ, 192000000U, 192, 3, 3, 0),
235 PLL_36XX_RATE(24 * MHZ, 166000000U, 166, 3, 3, 0),
236 PLL_36XX_RATE(24 * MHZ, 133000000U, 266, 3, 4, 0),
237 PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),
238 PLL_36XX_RATE(24 * MHZ, 66000000U, 176, 2, 5, 0),
[all …]
Dclk-exynos5420.c1332 PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0),
1333 PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0),
1334 PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0),
1335 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
1336 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
1337 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
1338 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
1339 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
1340 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1),
1341 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
[all …]
Dclk-exynos5433.c706 PLL_35XX_RATE(24 * MHZ, 2500000000U, 625, 6, 0),
707 PLL_35XX_RATE(24 * MHZ, 2400000000U, 500, 5, 0),
708 PLL_35XX_RATE(24 * MHZ, 2300000000U, 575, 6, 0),
709 PLL_35XX_RATE(24 * MHZ, 2200000000U, 550, 6, 0),
710 PLL_35XX_RATE(24 * MHZ, 2100000000U, 350, 4, 0),
711 PLL_35XX_RATE(24 * MHZ, 2000000000U, 500, 6, 0),
712 PLL_35XX_RATE(24 * MHZ, 1900000000U, 475, 6, 0),
713 PLL_35XX_RATE(24 * MHZ, 1800000000U, 375, 5, 0),
714 PLL_35XX_RATE(24 * MHZ, 1700000000U, 425, 6, 0),
715 PLL_35XX_RATE(24 * MHZ, 1600000000U, 400, 6, 0),
[all …]
/Linux-v4.19/Documentation/media/uapi/dvb/
Dfe-bandwidth-t.rst30 - .. _BANDWIDTH-1-712-MHZ:
38 - .. _BANDWIDTH-5-MHZ:
46 - .. _BANDWIDTH-6-MHZ:
54 - .. _BANDWIDTH-7-MHZ:
62 - .. _BANDWIDTH-8-MHZ:
70 - .. _BANDWIDTH-10-MHZ:
/Linux-v4.19/drivers/clk/
Dclk-nspire.c17 #define MHZ (1000 * 1000) macro
48 clk->base_clock = 48 * MHZ; in nspire_clkinfo_cx()
50 clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ; in nspire_clkinfo_cx()
59 clk->base_clock = 27 * MHZ; in nspire_clkinfo_classic()
61 clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ; in nspire_clkinfo_classic()
136 info.base_clock / MHZ, in nspire_clk_setup()
137 info.base_clock / info.base_cpu_ratio / MHZ, in nspire_clk_setup()
138 info.base_clock / info.base_ahb_ratio / MHZ); in nspire_clk_setup()
/Linux-v4.19/drivers/net/can/softing/
Dsofting_cs.c37 #define MHZ (1000*1000) macro
44 .freq = 16 * MHZ, .max_brp = 32, .max_sjw = 4,
56 .freq = 16 * MHZ, .max_brp = 32, .max_sjw = 4,
68 .freq = 20 * MHZ, .max_brp = 32, .max_sjw = 4,
80 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
92 .freq = 16 * MHZ, .max_brp = 64, .max_sjw = 4,
104 .freq = 20 * MHZ, .max_brp = 32, .max_sjw = 4,
116 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
128 .freq = 16 * MHZ, .max_brp = 64, .max_sjw = 4,
140 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
/Linux-v4.19/Documentation/devicetree/bindings/spi/
Dspi-mt65xx.txt22 - <&clk26m>: specify parent clock 26MHZ.
23 - <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ.
25 - <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ.
26 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
27 - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
/Linux-v4.19/arch/arm/mach-s3c64xx/
Dsetup-usb-phy.c31 case 12 * MHZ: in s3c_usb_otgphy_init()
34 case 24 * MHZ: in s3c_usb_otgphy_init()
38 case 48 * MHZ: in s3c_usb_otgphy_init()
/Linux-v4.19/arch/mips/ralink/
Dmt7620.c381 #define MHZ(x) ((x) * 1000 * 1000) macro
390 return MHZ(40); in mt7620_get_xtal_rate()
392 return MHZ(20); in mt7620_get_xtal_rate()
404 return MHZ(40); in mt7620_get_periph_rate()
421 return MHZ(600); in mt7620_get_cpu_pll_rate()
447 return MHZ(480); in mt7620_get_pll_rate()
525 if (xtal_rate == MHZ(40)) in ralink_clk_init()
526 cpu_rate = MHZ(580); in ralink_clk_init()
528 cpu_rate = MHZ(575); in ralink_clk_init()
530 periph_rate = MHZ(40); in ralink_clk_init()
[all …]
/Linux-v4.19/drivers/soc/xilinx/
Dxlnx_vcu.c88 #define MHZ 1000000 macro
89 #define FVCO_MIN (1500U * MHZ)
90 #define FVCO_MAX (3000U * MHZ)
94 #define LIMIT (10 * MHZ)
305 coreclk = xvcu_read(xvcu->logicore_reg_ba, VCU_CORE_CLK) * MHZ; in xvcu_set_vcu_pll_info()
306 mcuclk = xvcu_read(xvcu->logicore_reg_ba, VCU_MCU_CLK) * MHZ; in xvcu_set_vcu_pll_info()
312 refclk = (inte * MHZ) + (deci * (MHZ / FRAC)); in xvcu_set_vcu_pll_info()
/Linux-v4.19/drivers/clk/sirf/
Dclk-common.c13 #define MHZ (KHZ * KHZ) macro
91 WARN_ON(fin % MHZ); in pll_clk_recalc_rate()
92 return fin / MHZ * nf / nr / od * MHZ; in pll_clk_recalc_rate()
106 rate = rate - rate % MHZ; in pll_clk_round_rate()
108 nf = rate / MHZ; in pll_clk_round_rate()
116 nr = fin / MHZ; in pll_clk_round_rate()
138 nf = rate / MHZ; in pll_clk_set_rate()
139 if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1)) in pll_clk_set_rate()
143 BUG_ON(fin < MHZ); in pll_clk_set_rate()
145 nr = fin / MHZ; in pll_clk_set_rate()
[all …]
/Linux-v4.19/drivers/clk/mediatek/
Dclk-mt2701.c38 108 * MHZ),
40 400 * MHZ),
44 340 * MHZ),
46 340 * MHZ),
48 340 * MHZ),
50 27 * MHZ),
52 416 * MHZ),
54 143 * MHZ),
56 27 * MHZ),
928 #define MT8590_PLL_FMAX (2000 * MHZ)
/Linux-v4.19/arch/arm/plat-samsung/include/plat/
Dcpu.h80 #ifndef MHZ
81 #define MHZ (1000*1000) macro
84 #define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000)
/Linux-v4.19/drivers/phy/samsung/
Dphy-exynos4x12-usb2.c143 case 10 * MHZ: in exynos4x12_rate_to_clk()
146 case 12 * MHZ: in exynos4x12_rate_to_clk()
152 case 20 * MHZ: in exynos4x12_rate_to_clk()
155 case 24 * MHZ: in exynos4x12_rate_to_clk()
158 case 50 * MHZ: in exynos4x12_rate_to_clk()
Dphy-exynos5250-usb2.c153 case 10 * MHZ: in exynos5250_rate_to_clk()
156 case 12 * MHZ: in exynos5250_rate_to_clk()
162 case 20 * MHZ: in exynos5250_rate_to_clk()
165 case 24 * MHZ: in exynos5250_rate_to_clk()
168 case 50 * MHZ: in exynos5250_rate_to_clk()
Dphy-s5pv210-usb2.c76 case 12 * MHZ: in s5pv210_rate_to_clk()
79 case 24 * MHZ: in s5pv210_rate_to_clk()
82 case 48 * MHZ: in s5pv210_rate_to_clk()
/Linux-v4.19/drivers/gpu/drm/exynos/
Dexynos_drm_dsi.c536 #ifndef MHZ
537 #define MHZ (1000*1000) macro
551 p_min = DIV_ROUND_UP(fin, (12 * MHZ)); in exynos_dsi_pll_find_pms()
552 p_max = fin / (6 * MHZ); in exynos_dsi_pll_find_pms()
567 if (tmp < 500 * MHZ || in exynos_dsi_pll_find_pms()
568 tmp > driver_data->max_freq * MHZ) in exynos_dsi_pll_find_pms()
620 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, in exynos_dsi_set_pll()
621 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, in exynos_dsi_set_pll()
622 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, in exynos_dsi_set_pll()
623 770 * MHZ, 870 * MHZ, 950 * MHZ, in exynos_dsi_set_pll()
[all …]
/Linux-v4.19/arch/powerpc/boot/
Dredboot-8xx.c22 #define MHZ(x) ((x + 500000) / 1000000) macro
35 bd.bi_busfreq, MHZ(bd.bi_busfreq)); in platform_fixups()
Dredboot-83xx.c23 #define MHZ(x) ((x + 500000) / 1000000) macro
36 bd.bi_busfreq, MHZ(bd.bi_busfreq)); in platform_fixups()
/Linux-v4.19/drivers/clk/hisilicon/
Dclk-hi3660-stub.c34 #define MHZ (1000 * 1000) macro
75 stub_clk->rate = readl(freq_reg + (stub_clk->id << 2)) * MHZ; in hi3660_stub_clk_recalc_rate()
95 stub_clk->msg[1] = rate / MHZ; in hi3660_stub_clk_set_rate()

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