Searched refs:IMX7D_PLL_ENET_MAIN_100M_CLK (Results 1 – 8 of 8) sorted by relevance
138 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,144 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
44 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;70 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
180 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;207 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
68 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
124 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
111 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
56 #define IMX7D_PLL_ENET_MAIN_100M_CLK 43 macro
495 …clks[IMX7D_PLL_ENET_MAIN_100M_CLK] = imx_clk_gate("pll_enet_100m_clk", "pll_enet_100m", base + 0xe… in imx7d_clocks_init()
