1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Copyright (C) 2015 Freescale Semiconductor, Inc.
4
5/dts-v1/;
6
7#include "imx7d.dtsi"
8
9/ {
10	model = "Freescale i.MX7 SabreSD Board";
11	compatible = "fsl,imx7d-sdb", "fsl,imx7d";
12
13	chosen {
14		stdout-path = &uart1;
15	};
16
17	memory@80000000 {
18		reg = <0x80000000 0x80000000>;
19	};
20
21	gpio-keys {
22		compatible = "gpio-keys";
23		pinctrl-names = "default";
24		pinctrl-0 = <&pinctrl_gpio_keys>;
25
26		volume-up {
27			label = "Volume Up";
28			gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
29			linux,code = <KEY_VOLUMEUP>;
30		};
31
32		volume-down {
33			label = "Volume Down";
34			gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
35			linux,code = <KEY_VOLUMEDOWN>;
36		};
37	};
38
39	spi4 {
40		compatible = "spi-gpio";
41		pinctrl-names = "default";
42		pinctrl-0 = <&pinctrl_spi4>;
43		gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
44		gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
45		cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
46		num-chipselects = <1>;
47		#address-cells = <1>;
48		#size-cells = <0>;
49
50		extended_io: gpio-expander@0 {
51			compatible = "fairchild,74hc595";
52			gpio-controller;
53			#gpio-cells = <2>;
54			reg = <0>;
55			registers-number = <1>;
56			spi-max-frequency = <100000>;
57		};
58	};
59
60	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
61		compatible = "regulator-fixed";
62		regulator-name = "usb_otg1_vbus";
63		regulator-min-microvolt = <5000000>;
64		regulator-max-microvolt = <5000000>;
65		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
66		enable-active-high;
67	};
68
69	reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
70		compatible = "regulator-fixed";
71		regulator-name = "usb_otg2_vbus";
72		regulator-min-microvolt = <5000000>;
73		regulator-max-microvolt = <5000000>;
74		gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
75		enable-active-high;
76	};
77
78	reg_vref_1v8: regulator-vref-1v8 {
79		compatible = "regulator-fixed";
80		regulator-name = "vref-1v8";
81		regulator-min-microvolt = <1800000>;
82		regulator-max-microvolt = <1800000>;
83	};
84
85	reg_brcm: regulator-brcm {
86		compatible = "regulator-fixed";
87		gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
88		enable-active-high;
89		regulator-name = "brcm_reg";
90		pinctrl-names = "default";
91		pinctrl-0 = <&pinctrl_brcm_reg>;
92		regulator-min-microvolt = <3300000>;
93		regulator-max-microvolt = <3300000>;
94		startup-delay-us = <200000>;
95	};
96
97	reg_lcd_3v3: regulator-lcd-3v3 {
98		compatible = "regulator-fixed";
99		regulator-name = "lcd-3v3";
100		regulator-min-microvolt = <3300000>;
101		regulator-max-microvolt = <3300000>;
102		gpio = <&extended_io 7 GPIO_ACTIVE_LOW>;
103	};
104
105	reg_can2_3v3: regulator-can2-3v3 {
106		compatible = "regulator-fixed";
107		regulator-name = "can2-3v3";
108		pinctrl-names = "default";
109		pinctrl-0 = <&pinctrl_flexcan2_reg>;
110		regulator-min-microvolt = <3300000>;
111		regulator-max-microvolt = <3300000>;
112		gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
113	};
114
115	backlight: backlight {
116		compatible = "pwm-backlight";
117		pwms = <&pwm1 0 5000000 0>;
118		brightness-levels = <0 4 8 16 32 64 128 255>;
119		default-brightness-level = <6>;
120		status = "okay";
121	};
122
123	panel {
124		compatible = "innolux,at043tn24";
125		backlight = <&backlight>;
126		power-supply = <&reg_lcd_3v3>;
127
128		port {
129			panel_in: endpoint {
130				remote-endpoint = <&display_out>;
131			};
132		};
133	};
134};
135
136&adc1 {
137	vref-supply = <&reg_vref_1v8>;
138	status = "okay";
139};
140
141&adc2 {
142	vref-supply = <&reg_vref_1v8>;
143	status = "okay";
144};
145
146&cpu0 {
147	cpu-supply = <&sw1a_reg>;
148};
149
150&ecspi3 {
151	pinctrl-names = "default";
152	pinctrl-0 = <&pinctrl_ecspi3>;
153	cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
154	status = "okay";
155
156	tsc2046@0 {
157		compatible = "ti,tsc2046";
158		reg = <0>;
159		spi-max-frequency = <1000000>;
160		pinctrl-names ="default";
161		pinctrl-0 = <&pinctrl_tsc2046_pendown>;
162		interrupt-parent = <&gpio2>;
163		interrupts = <29 0>;
164		pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
165		ti,x-min = /bits/ 16 <0>;
166		ti,x-max = /bits/ 16 <0>;
167		ti,y-min = /bits/ 16 <0>;
168		ti,y-max = /bits/ 16 <0>;
169		ti,pressure-max = /bits/ 16 <0>;
170		ti,x-plate-ohms = /bits/ 16 <400>;
171		wakeup-source;
172	};
173};
174
175&fec1 {
176	pinctrl-names = "default";
177	pinctrl-0 = <&pinctrl_enet1>;
178	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
179			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
180	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
181	assigned-clock-rates = <0>, <100000000>;
182	phy-mode = "rgmii";
183	phy-handle = <&ethphy0>;
184	fsl,magic-packet;
185	phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>;
186	status = "okay";
187
188	mdio {
189		#address-cells = <1>;
190		#size-cells = <0>;
191
192		ethphy0: ethernet-phy@0 {
193			reg = <0>;
194		};
195
196		ethphy1: ethernet-phy@1 {
197			reg = <1>;
198		};
199	};
200};
201
202&fec2 {
203	pinctrl-names = "default";
204	pinctrl-0 = <&pinctrl_enet2>;
205	assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
206			  <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
207	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
208	assigned-clock-rates = <0>, <100000000>;
209	phy-mode = "rgmii";
210	phy-handle = <&ethphy1>;
211	fsl,magic-packet;
212	status = "okay";
213};
214
215&flexcan2 {
216	pinctrl-names = "default";
217	pinctrl-0 = <&pinctrl_flexcan2>;
218	xceiver-supply = <&reg_can2_3v3>;
219	status = "okay";
220};
221
222&i2c1 {
223	pinctrl-names = "default";
224	pinctrl-0 = <&pinctrl_i2c1>;
225	status = "okay";
226
227	pmic: pfuze3000@8 {
228		compatible = "fsl,pfuze3000";
229		reg = <0x08>;
230
231		regulators {
232			sw1a_reg: sw1a {
233				regulator-min-microvolt = <700000>;
234				regulator-max-microvolt = <1475000>;
235				regulator-boot-on;
236				regulator-always-on;
237				regulator-ramp-delay = <6250>;
238			};
239
240			/* use sw1c_reg to align with pfuze100/pfuze200 */
241			sw1c_reg: sw1b {
242				regulator-min-microvolt = <700000>;
243				regulator-max-microvolt = <1475000>;
244				regulator-boot-on;
245				regulator-always-on;
246				regulator-ramp-delay = <6250>;
247			};
248
249			sw2_reg: sw2 {
250				regulator-min-microvolt = <1500000>;
251				regulator-max-microvolt = <1850000>;
252				regulator-boot-on;
253				regulator-always-on;
254			};
255
256			sw3a_reg: sw3 {
257				regulator-min-microvolt = <900000>;
258				regulator-max-microvolt = <1650000>;
259				regulator-boot-on;
260				regulator-always-on;
261			};
262
263			swbst_reg: swbst {
264				regulator-min-microvolt = <5000000>;
265				regulator-max-microvolt = <5150000>;
266			};
267
268			snvs_reg: vsnvs {
269				regulator-min-microvolt = <1000000>;
270				regulator-max-microvolt = <3000000>;
271				regulator-boot-on;
272				regulator-always-on;
273			};
274
275			vref_reg: vrefddr {
276				regulator-boot-on;
277				regulator-always-on;
278			};
279
280			vgen1_reg: vldo1 {
281				regulator-min-microvolt = <1800000>;
282				regulator-max-microvolt = <3300000>;
283				regulator-always-on;
284			};
285
286			vgen2_reg: vldo2 {
287				regulator-min-microvolt = <800000>;
288				regulator-max-microvolt = <1550000>;
289			};
290
291			vgen3_reg: vccsd {
292				regulator-min-microvolt = <2850000>;
293				regulator-max-microvolt = <3300000>;
294				regulator-always-on;
295			};
296
297			vgen4_reg: v33 {
298				regulator-min-microvolt = <2850000>;
299				regulator-max-microvolt = <3300000>;
300				regulator-always-on;
301			};
302
303			vgen5_reg: vldo3 {
304				regulator-min-microvolt = <1800000>;
305				regulator-max-microvolt = <3300000>;
306				regulator-always-on;
307			};
308
309			vgen6_reg: vldo4 {
310				regulator-min-microvolt = <2800000>;
311				regulator-max-microvolt = <2800000>;
312				regulator-always-on;
313			};
314		};
315	};
316};
317
318&i2c2 {
319	pinctrl-names = "default";
320	pinctrl-0 = <&pinctrl_i2c2>;
321	status = "okay";
322
323	mpl3115@60 {
324		compatible = "fsl,mpl3115";
325		reg = <0x60>;
326	};
327};
328
329&i2c3 {
330	pinctrl-names = "default";
331	pinctrl-0 = <&pinctrl_i2c3>;
332	status = "okay";
333};
334
335&i2c4 {
336	pinctrl-names = "default";
337	pinctrl-0 = <&pinctrl_i2c4>;
338	status = "okay";
339
340	codec: wm8960@1a {
341		compatible = "wlf,wm8960";
342		reg = <0x1a>;
343		clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
344		clock-names = "mclk";
345		wlf,shared-lrclk;
346	};
347};
348
349&lcdif {
350	pinctrl-names = "default";
351	pinctrl-0 = <&pinctrl_lcdif>;
352	status = "okay";
353
354	port {
355		display_out: endpoint {
356			remote-endpoint = <&panel_in>;
357		};
358	};
359};
360
361&pcie {
362	reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
363	status = "okay";
364};
365
366&uart1 {
367	pinctrl-names = "default";
368	pinctrl-0 = <&pinctrl_uart1>;
369	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
370	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
371	status = "okay";
372};
373
374&uart6 {
375	pinctrl-names = "default";
376	pinctrl-0 = <&pinctrl_uart6>;
377	assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
378	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
379	uart-has-rtscts;
380	status = "okay";
381};
382
383&usbotg1 {
384	vbus-supply = <&reg_usb_otg1_vbus>;
385	status = "okay";
386};
387
388&usbotg2 {
389	vbus-supply = <&reg_usb_otg2_vbus>;
390	dr_mode = "host";
391	status = "okay";
392};
393
394&usdhc1 {
395	pinctrl-names = "default";
396	pinctrl-0 = <&pinctrl_usdhc1>;
397	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
398	wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
399	wakeup-source;
400	keep-power-in-suspend;
401	status = "okay";
402};
403
404&usdhc2 {
405	pinctrl-names = "default", "state_100mhz", "state_200mhz";
406	pinctrl-0 = <&pinctrl_usdhc2>;
407	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
408	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
409	wakeup-source;
410	keep-power-in-suspend;
411	non-removable;
412	vmmc-supply = <&reg_brcm>;
413	fsl,tuning-step = <2>;
414	status = "okay";
415};
416
417&usdhc3 {
418	pinctrl-names = "default", "state_100mhz", "state_200mhz";
419	pinctrl-0 = <&pinctrl_usdhc3>;
420	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
421	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
422	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
423	assigned-clock-rates = <400000000>;
424	bus-width = <8>;
425	fsl,tuning-step = <2>;
426	non-removable;
427	status = "okay";
428};
429
430&wdog1 {
431	pinctrl-names = "default";
432	pinctrl-0 = <&pinctrl_wdog>;
433	fsl,ext-reset-output;
434};
435
436&iomuxc {
437	pinctrl-names = "default";
438	pinctrl-0 = <&pinctrl_hog>;
439
440	imx7d-sdb {
441		pinctrl_brcm_reg: brcmreggrp {
442			fsl,pins = <
443				MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21	0x14
444			>;
445		};
446
447		pinctrl_ecspi3: ecspi3grp {
448			fsl,pins = <
449				MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO	0x2
450				MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI	0x2
451				MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK	0x2
452				MX7D_PAD_SD2_CD_B__GPIO5_IO9		0x59
453			>;
454		};
455
456		pinctrl_enet1: enet1grp {
457			fsl,pins = <
458				MX7D_PAD_GPIO1_IO10__ENET1_MDIO			0x3
459				MX7D_PAD_GPIO1_IO11__ENET1_MDC			0x3
460				MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC	0x1
461				MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0	0x1
462				MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1	0x1
463				MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2	0x1
464				MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3	0x1
465				MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x1
466				MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC	0x1
467				MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0	0x1
468				MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1	0x1
469				MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2	0x1
470				MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3	0x1
471				MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x1
472			>;
473		};
474
475		pinctrl_enet2: enet2grp {
476			fsl,pins = <
477				MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC		0x1
478				MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0		0x1
479				MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1		0x1
480				MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2		0x1
481				MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3		0x1
482				MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL		0x1
483				MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC		0x1
484				MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0		0x1
485				MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1		0x1
486				MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2		0x1
487				MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3		0x1
488				MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL		0x1
489			>;
490		};
491
492		pinctrl_flexcan2: flexcan2grp {
493			fsl,pins = <
494				MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX	0x59
495				MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX	0x59
496			>;
497		};
498
499		pinctrl_flexcan2_reg: flexcan2reggrp {
500			fsl,pins = <
501				MX7D_PAD_EPDC_DATA14__GPIO2_IO14	0x59	/* CAN_STBY */
502			>;
503		};
504
505		pinctrl_gpio_keys: gpio_keysgrp {
506			fsl,pins = <
507				MX7D_PAD_SD2_RESET_B__GPIO5_IO11	0x59
508				MX7D_PAD_SD2_WP__GPIO5_IO10		0x59
509			>;
510		};
511
512		pinctrl_hog: hoggrp {
513			fsl,pins = <
514				MX7D_PAD_UART3_CTS_B__GPIO4_IO7		0x14
515				MX7D_PAD_ECSPI2_SS0__GPIO4_IO23		0x34  /* bt reg on */
516			>;
517		};
518
519		pinctrl_i2c1: i2c1grp {
520			fsl,pins = <
521				MX7D_PAD_I2C1_SDA__I2C1_SDA		0x4000007f
522				MX7D_PAD_I2C1_SCL__I2C1_SCL		0x4000007f
523			>;
524		};
525
526		pinctrl_i2c2: i2c2grp {
527			fsl,pins = <
528				MX7D_PAD_I2C2_SDA__I2C2_SDA		0x4000007f
529				MX7D_PAD_I2C2_SCL__I2C2_SCL		0x4000007f
530			>;
531		};
532
533		pinctrl_i2c3: i2c3grp {
534			fsl,pins = <
535				MX7D_PAD_I2C3_SDA__I2C3_SDA		0x4000007f
536				MX7D_PAD_I2C3_SCL__I2C3_SCL		0x4000007f
537			>;
538		};
539
540		pinctrl_i2c4: i2c4grp {
541			fsl,pins = <
542				MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA		0x4000007f
543				MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL		0x4000007f
544			>;
545		};
546
547		pinctrl_lcdif: lcdifgrp {
548			fsl,pins = <
549				MX7D_PAD_LCD_DATA00__LCD_DATA0		0x79
550				MX7D_PAD_LCD_DATA01__LCD_DATA1		0x79
551				MX7D_PAD_LCD_DATA02__LCD_DATA2		0x79
552				MX7D_PAD_LCD_DATA03__LCD_DATA3		0x79
553				MX7D_PAD_LCD_DATA04__LCD_DATA4		0x79
554				MX7D_PAD_LCD_DATA05__LCD_DATA5		0x79
555				MX7D_PAD_LCD_DATA06__LCD_DATA6		0x79
556				MX7D_PAD_LCD_DATA07__LCD_DATA7		0x79
557				MX7D_PAD_LCD_DATA08__LCD_DATA8		0x79
558				MX7D_PAD_LCD_DATA09__LCD_DATA9		0x79
559				MX7D_PAD_LCD_DATA10__LCD_DATA10		0x79
560				MX7D_PAD_LCD_DATA11__LCD_DATA11		0x79
561				MX7D_PAD_LCD_DATA12__LCD_DATA12		0x79
562				MX7D_PAD_LCD_DATA13__LCD_DATA13		0x79
563				MX7D_PAD_LCD_DATA14__LCD_DATA14		0x79
564				MX7D_PAD_LCD_DATA15__LCD_DATA15		0x79
565				MX7D_PAD_LCD_DATA16__LCD_DATA16		0x79
566				MX7D_PAD_LCD_DATA17__LCD_DATA17		0x79
567				MX7D_PAD_LCD_DATA18__LCD_DATA18		0x79
568				MX7D_PAD_LCD_DATA19__LCD_DATA19		0x79
569				MX7D_PAD_LCD_DATA20__LCD_DATA20		0x79
570				MX7D_PAD_LCD_DATA21__LCD_DATA21		0x79
571				MX7D_PAD_LCD_DATA22__LCD_DATA22		0x79
572				MX7D_PAD_LCD_DATA23__LCD_DATA23		0x79
573				MX7D_PAD_LCD_CLK__LCD_CLK		0x79
574				MX7D_PAD_LCD_ENABLE__LCD_ENABLE		0x79
575				MX7D_PAD_LCD_VSYNC__LCD_VSYNC		0x79
576				MX7D_PAD_LCD_HSYNC__LCD_HSYNC		0x79
577				MX7D_PAD_LCD_RESET__LCD_RESET		0x79
578			>;
579		};
580
581		pinctrl_spi4: spi4grp {
582			fsl,pins = <
583				MX7D_PAD_GPIO1_IO09__GPIO1_IO9	0x59
584				MX7D_PAD_GPIO1_IO12__GPIO1_IO12	0x59
585				MX7D_PAD_GPIO1_IO13__GPIO1_IO13	0x59
586			>;
587		};
588
589		pinctrl_tsc2046_pendown: tsc2046_pendown {
590			fsl,pins = <
591				MX7D_PAD_EPDC_BDR1__GPIO2_IO29		0x59
592			>;
593		};
594
595		pinctrl_uart1: uart1grp {
596			fsl,pins = <
597				MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX	0x79
598				MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX	0x79
599			>;
600		};
601
602		pinctrl_uart5: uart5grp {
603			fsl,pins = <
604				MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX	0x79
605				MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX	0x79
606				MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS	0x79
607				MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS	0x79
608			>;
609		};
610
611		pinctrl_uart6: uart6grp {
612			fsl,pins = <
613				MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX	0x79
614				MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX	0x79
615				MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS	0x79
616				MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS	0x79
617			>;
618		};
619
620		pinctrl_usdhc1: usdhc1grp {
621			fsl,pins = <
622				MX7D_PAD_SD1_CMD__SD1_CMD		0x59
623				MX7D_PAD_SD1_CLK__SD1_CLK		0x19
624				MX7D_PAD_SD1_DATA0__SD1_DATA0		0x59
625				MX7D_PAD_SD1_DATA1__SD1_DATA1		0x59
626				MX7D_PAD_SD1_DATA2__SD1_DATA2		0x59
627				MX7D_PAD_SD1_DATA3__SD1_DATA3		0x59
628				MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x59 /* CD */
629				MX7D_PAD_SD1_WP__GPIO5_IO1		0x59 /* WP */
630				MX7D_PAD_SD1_RESET_B__GPIO5_IO2		0x59 /* vmmc */
631			>;
632		};
633
634		pinctrl_usdhc2: usdhc2grp {
635			fsl,pins = <
636				MX7D_PAD_SD2_CMD__SD2_CMD		0x59
637				MX7D_PAD_SD2_CLK__SD2_CLK		0x19
638				MX7D_PAD_SD2_DATA0__SD2_DATA0		0x59
639				MX7D_PAD_SD2_DATA1__SD2_DATA1		0x59
640				MX7D_PAD_SD2_DATA2__SD2_DATA2		0x59
641				MX7D_PAD_SD2_DATA3__SD2_DATA3		0x59
642			>;
643		};
644
645		pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
646			fsl,pins = <
647				MX7D_PAD_SD2_CMD__SD2_CMD		0x5a
648				MX7D_PAD_SD2_CLK__SD2_CLK		0x1a
649				MX7D_PAD_SD2_DATA0__SD2_DATA0		0x5a
650				MX7D_PAD_SD2_DATA1__SD2_DATA1		0x5a
651				MX7D_PAD_SD2_DATA2__SD2_DATA2		0x5a
652				MX7D_PAD_SD2_DATA3__SD2_DATA3		0x5a
653			>;
654		};
655
656		pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
657			fsl,pins = <
658				MX7D_PAD_SD2_CMD__SD2_CMD		0x5b
659				MX7D_PAD_SD2_CLK__SD2_CLK		0x1b
660				MX7D_PAD_SD2_DATA0__SD2_DATA0		0x5b
661				MX7D_PAD_SD2_DATA1__SD2_DATA1		0x5b
662				MX7D_PAD_SD2_DATA2__SD2_DATA2		0x5b
663				MX7D_PAD_SD2_DATA3__SD2_DATA3		0x5b
664			>;
665		};
666
667
668		pinctrl_usdhc3: usdhc3grp {
669			fsl,pins = <
670				MX7D_PAD_SD3_CMD__SD3_CMD		0x59
671				MX7D_PAD_SD3_CLK__SD3_CLK		0x19
672				MX7D_PAD_SD3_DATA0__SD3_DATA0		0x59
673				MX7D_PAD_SD3_DATA1__SD3_DATA1		0x59
674				MX7D_PAD_SD3_DATA2__SD3_DATA2		0x59
675				MX7D_PAD_SD3_DATA3__SD3_DATA3		0x59
676				MX7D_PAD_SD3_DATA4__SD3_DATA4		0x59
677				MX7D_PAD_SD3_DATA5__SD3_DATA5		0x59
678				MX7D_PAD_SD3_DATA6__SD3_DATA6		0x59
679				MX7D_PAD_SD3_DATA7__SD3_DATA7		0x59
680				MX7D_PAD_SD3_STROBE__SD3_STROBE		0x19
681			>;
682		};
683
684		pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
685			fsl,pins = <
686				MX7D_PAD_SD3_CMD__SD3_CMD		0x5a
687				MX7D_PAD_SD3_CLK__SD3_CLK		0x1a
688				MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5a
689				MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5a
690				MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5a
691				MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5a
692				MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5a
693				MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5a
694				MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5a
695				MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5a
696				MX7D_PAD_SD3_STROBE__SD3_STROBE		0x1a
697			>;
698		};
699
700		pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
701			fsl,pins = <
702				MX7D_PAD_SD3_CMD__SD3_CMD		0x5b
703				MX7D_PAD_SD3_CLK__SD3_CLK		0x1b
704				MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5b
705				MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5b
706				MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5b
707				MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5b
708				MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5b
709				MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5b
710				MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5b
711				MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5b
712				MX7D_PAD_SD3_STROBE__SD3_STROBE		0x1b
713			>;
714		};
715	};
716};
717
718&pwm1 {
719	pinctrl-names = "default";
720	pinctrl-0 = <&pinctrl_pwm1>;
721	status = "okay";
722};
723
724&iomuxc_lpsr {
725	pinctrl_wdog: wdoggrp {
726		fsl,pins = <
727			MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B		0x74
728		>;
729	};
730
731	pinctrl_pwm1: pwm1grp {
732		fsl,pins = <
733			MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT		0x30
734		>;
735	};
736};
737