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Searched refs:DRAM (Results 1 – 25 of 54) sorted by relevance

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/Linux-v4.19/Documentation/devicetree/bindings/devfreq/
Drk3399_dmc.txt39 clocks freq is half of DRAM clock), default
56 The controller, pi, PHY and DRAM clock will
70 - rockchip,ddr3_odt_dis_freq : When the DRAM type is DDR3, this parameter defines
73 the ODT on the DRAM side and controller side are
76 - rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines
77 the DRAM side driver strength in ohms. Default
80 - rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines
81 the DRAM side ODT strength in ohms. Default value
84 - rockchip,phy_ddr3_ca_drv : When the DRAM type is DDR3, this parameter defines
89 - rockchip,phy_ddr3_dq_drv : When the DRAM type is DDR3, this parameter defines
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Dexynos-bus.txt3 The Samsung Exynos SoC has many buses for data transfer between DRAM
108 VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller)
143 transfer data between DRAM and CPU and uses the VDD_MIF regulator.
/Linux-v4.19/sound/isa/gus/
Dgus_dram.c43 outsb(GUSP(gus, DRAM), buffer, size1); in snd_gus_dram_poke()
79 insb(GUSP(gus, DRAM), buffer, size1); in snd_gus_dram_peek()
/Linux-v4.19/arch/arm/
DKconfig-nommu14 hex '(S)DRAM Base Address' if SET_MEM_PARAM
18 hex '(S)DRAM SIZE' if SET_MEM_PARAM
/Linux-v4.19/arch/arm64/boot/dts/broadcom/stingray/
Dstingray-board-base.dtsi22 &memory { /* Default DRAM banks */
/Linux-v4.19/drivers/memory/tegra/
DKconfig15 Tegra124 chips. The EMC controls the external DRAM on the board.
/Linux-v4.19/Documentation/x86/
Damd-memory-encryption.txt6 automatically decrypted when read from DRAM and encrypted when written to
7 DRAM. SME can therefore be used to protect the contents of DRAM from physical
/Linux-v4.19/arch/arm/mach-lpc32xx/
Dsuspend.S54 @ This guarantees a small windows where DRAM isn't busy
/Linux-v4.19/arch/x86/ras/
DKconfig13 have ECC DIMMs and doesn't have DRAM ECC checking enabled in the BIOS.
/Linux-v4.19/Documentation/arm/SA1100/
DLART5 applications. It has 32 MB DRAM, 4MB Flash ROM, double RS232 and all
DItsy11 64 Meg of DRAM and 32 Meg of Flash. The initial work includes support for
/Linux-v4.19/Documentation/devicetree/bindings/nds32/
Datl2c.txt7 reducing DRAM accesses.
/Linux-v4.19/Documentation/devicetree/bindings/clock/
Dsun9i-de.txt12 - "dram": the DRAM bus clock for the system
/Linux-v4.19/Documentation/driver-api/
Dedac.rst18 The individual DRAM chips on a memory stick. These devices commonly
69 This is the name of the DRAM signal used to select the DRAM ranks to be
/Linux-v4.19/Documentation/devicetree/bindings/arm/
Dfw-cfg.txt12 DTB that QEMU places at the bottom of the guest's DRAM.
/Linux-v4.19/drivers/edac/
DKconfig81 Support for error detection and correction of DRAM ECC errors on
91 errors into DRAM.
101 which trigger the DRAM ECC Read and Write respectively.
165 E3-1200 based DRAM controllers.
353 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
/Linux-v4.19/drivers/powercap/
DKconfig28 fine grained control. These domains include processor package, DRAM
/Linux-v4.19/arch/c6x/kernel/
Dvectors.S12 ; At RESET the processor sets up the DRAM timing parameters and
/Linux-v4.19/arch/arm/boot/dts/
Dberlin2cd-valve-steamlink.dts43 * DRAM (providing 1.35V). The other regulator on the opposite side
Dimx6ul-pico-hobbit.dts204 /* DRAM */
212 /* DRAM */
/Linux-v4.19/Documentation/devicetree/bindings/net/
Dmarvell-neta-bm.txt13 in DRAM. Can be set for each pool (id 0 : 3) separately. The value has
/Linux-v4.19/arch/arm/mach-sa1100/
Dsleep.S133 @ Step 5 clear DRAM refresh control register
/Linux-v4.19/arch/arm/mach-tegra/
Dsleep-tegra20.S396 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
504 str r2, [r1, #EMC_REQ_CTRL] @ stall incoming DRAM requests
/Linux-v4.19/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra20-pmc.txt33 0 (LP0): CPU + Core voltage off and DRAM in self-refresh
34 1 (LP1): CPU voltage off and DRAM in self-refresh
/Linux-v4.19/Documentation/ABI/testing/
Dsysfs-devices-edac101 Description: This attribute file will display what type of DRAM device is
110 mean a Chipkill with x4 DRAM.

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