Home
last modified time | relevance | path

Searched refs:DP_TP_CTL (Results 1 – 4 of 4) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/i915/
Dintel_ddi.c1152 I915_WRITE(DP_TP_CTL(PORT_E), in hsw_fdi_link_train()
1215 temp = I915_READ(DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()
1218 I915_WRITE(DP_TP_CTL(PORT_E), temp); in hsw_fdi_link_train()
1219 POSTING_READ(DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()
1232 I915_WRITE(DP_TP_CTL(PORT_E), in hsw_fdi_link_train()
2795 val = I915_READ(DP_TP_CTL(port)); in intel_disable_ddi_buf()
2798 I915_WRITE(DP_TP_CTL(port), val); in intel_disable_ddi_buf()
3082 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { in intel_ddi_prepare_link_retrain()
3090 val = I915_READ(DP_TP_CTL(port)); in intel_ddi_prepare_link_retrain()
3093 I915_WRITE(DP_TP_CTL(port), val); in intel_ddi_prepare_link_retrain()
[all …]
Dintel_dp.c2877 uint32_t temp = I915_READ(DP_TP_CTL(port)); in _intel_dp_set_link_train()
2903 I915_WRITE(DP_TP_CTL(port), temp); in _intel_dp_set_link_train()
3602 val = I915_READ(DP_TP_CTL(port)); in intel_dp_set_idle_link_train()
3605 I915_WRITE(DP_TP_CTL(port), val); in intel_dp_set_idle_link_train()
Di915_reg.h9031 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) macro
/Linux-v4.19/drivers/gpu/drm/i915/gvt/
Dhandlers.c563 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E)); in fdi_auto_training_started()
682 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E))
2394 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2395 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2396 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2397 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2398 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()