| /Linux-v4.19/Documentation/devicetree/bindings/mips/brcm/ |
| D | soc.txt | 45 independently (control registers, DDR PHYs, etc.). One might consider
58 the entire memory controller (including all sub nodes: DDR PHY,
86 == DDR PHY control
88 Control registers for this memory controller's DDR PHY.
95 - reg : the DDR PHY register range and length
104 == DDR memory controller sequencer
106 Control registers for this memory controller's DDR memory sequencer
115 - reg : the DDR sequencer register range and length
136 - reg : the DDR Arbiter register range and length
|
| /Linux-v4.19/Documentation/devicetree/bindings/memory-controllers/ |
| D | calxeda-ddr-ctrlr.txt | 1 Calxeda DDR memory controller
7 - reg : Address and size for DDR controller registers.
8 - interrupts : Interrupt for DDR controller.
|
| D | ath79-ddr-controller.txt | 1 Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller
3 The DDR controller of the AR7xxx and AR9xxx families provides an interface
4 to flush the FIFO between various devices and the DDR. This is mainly used
|
| D | brcm,dpfe-cpu.txt | 1 DDR PHY Front End (DPFE) for Broadcom STB
5 communicate with the DCPU, which resides inside the DDR PHY.
|
| /Linux-v4.19/Documentation/devicetree/bindings/memory-controllers/fsl/ |
| D | ddr.txt | 1 Freescale DDR memory controller
8 - reg : Address and size of DDR controller registers
9 - interrupts : Error interrupt of DDR controller
|
| /Linux-v4.19/Documentation/ABI/testing/ |
| D | sysfs-driver-bd9571mwv-regulator | 5 Description: Read/write the current state of DDR Backup Mode, which controls
6 if DDR power rails will be kept powered during system suspend.
9 A. With a momentary power switch (or pulse signal), DDR
23 DDR Backup Mode must be explicitly enabled by the user,
|
| /Linux-v4.19/Documentation/devicetree/bindings/clock/ |
| D | mvebu-core-clock.txt | 12 4 = dramclk (DDR clock)
18 3 = ddrclk (DDR clock)
24 3 = ddrclk (DDR clock)
37 2 = ddrclk (DDR clock)
44 3 = ddrclk (DDR controller clock derived from CPU0 clock)
49 2 = ddrclk (DDR controller clock derived from CPU0 clock)
|
| D | brcm,bcm2835-cprman.txt | 25 - DSI0 DDR clock
28 - DSI1 DDR clock
|
| D | armada3700-periph-clock.txt | 26 11 ddr_phy DDR PHY
27 12 ddr_fclk DDR F clock
|
| D | qca,ath79-pll.txt | 3 The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
|
| /Linux-v4.19/drivers/gpio/ |
| D | gpio-mb86s7x.c | 35 #define DDR(x) (0x10 + x / 8 * 4) macro
87 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_input()
89 writel(val, gchip->base + DDR(gpio)); in mb86s70_gpio_direction_input()
112 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_output()
114 writel(val, gchip->base + DDR(gpio)); in mb86s70_gpio_direction_output()
|
| /Linux-v4.19/Documentation/devicetree/bindings/arm/bcm/ |
| D | brcm,brcmstb.txt | 148 independently (control registers, DDR PHYs, etc.). One might consider
163 == DDR PHY control
165 Control registers for this memory controller's DDR PHY.
175 - reg : the DDR PHY register range
177 == DDR SHIMPHY
179 Control registers for this memory controller's DDR SHIMPHY.
183 - reg : the DDR SHIMPHY register range
185 == MEMC DDR control
198 - reg : the MEMC DDR register range
|
| /Linux-v4.19/Documentation/devicetree/bindings/devfreq/ |
| D | rk3399_dmc.txt | 5 - devfreq-events: Node to get DDR loading, Refer to
19 It should be a DCF interrupt. When DDR DVFS finishes
22 Following properties relate to DDR timing:
61 When DDR frequency is less than DRAM_DLL_DISB_FREQ,
66 MHz (Mega Hz). When DDR frequency is less than
72 when the DDR frequency is less then ddr3_odt_dis_freq,
99 When DDR frequency is less then ddr3_odt_dis_freq,
127 MHz (Mega Hz). When the DDR frequency is less then
|
| /Linux-v4.19/drivers/mtd/lpddr/ |
| D | Kconfig | 9 flash chips. Synonymous with Mobile-DDR. It is a new standard for
10 DDR memories, intended for battery-operated systems.
|
| /Linux-v4.19/arch/arm/mach-omap2/ |
| D | sleep24xx.S | 69 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
89 movs r0, r0 @ see if DDR or SDR
|
| /Linux-v4.19/Documentation/devicetree/bindings/lpddr2/ |
| D | lpddr2-timings.txt | 5 - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
6 - max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
|
| /Linux-v4.19/drivers/memory/ |
| D | Kconfig | 19 bool "Atmel (Multi-port DDR-)SDRAM Controller"
24 DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
25 Starting with the at91sam9g45, this controller supports SDR, DDR and
26 LP-DDR memories.
54 select DDR
|
| /Linux-v4.19/Documentation/memory-devices/ |
| D | ti-emif.txt | 34 DDR device details and other board dependent and SoC dependent
36 - DDR device details: 'struct ddr_device_info'
|
| /Linux-v4.19/Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,imx7ulp-pinctrl.txt | 4 ports and IOMUXC DDR for DDR interface.
|
| /Linux-v4.19/Documentation/devicetree/bindings/mfd/ |
| D | bd9571mwv.txt | 28 - rohm,ddr-backup-power : Value to use for DDR-Backup Power (default 0).
29 This is a bitmask that specifies which DDR power
|
| /Linux-v4.19/Documentation/devicetree/bindings/mips/img/ |
| D | xilfpga.txt | 20 - 128Mbyte DDR RAM at 0x0000_0000
74 DDR initialization is already handled by a HW IP block.
|
| /Linux-v4.19/Documentation/arm/Samsung-S3C24XX/ |
| D | S3C2413.txt | 8 interface and mobile DDR memory support. See the S3C2412 support
|
| /Linux-v4.19/Documentation/devicetree/bindings/reset/ |
| D | amlogic,meson-axg-audio-arb.txt | 4 disables the access of Audio FIFOs to DDR on AXG based SoC.
|
| /Linux-v4.19/drivers/pinctrl/tegra/ |
| D | pinctrl-tegra30.c | 2211 …PINGROUP(vi_d1_pd5, DDR, SDMMC2, VI, RSVD4, 0x3128, N, …
2212 …PINGROUP(vi_vsync_pd6, DDR, RSVD2, VI, RSVD4, 0x315c, N, …
2213 …PINGROUP(vi_hsync_pd7, DDR, RSVD2, VI, RSVD4, 0x3160, N, …
2270 …PINGROUP(vi_d2_pl0, DDR, SDMMC2, VI, RSVD4, 0x312c, N, …
2271 …PINGROUP(vi_d3_pl1, DDR, SDMMC2, VI, RSVD4, 0x3130, N, …
2272 …PINGROUP(vi_d4_pl2, DDR, SDMMC2, VI, RSVD4, 0x3134, N, …
2273 …PINGROUP(vi_d5_pl3, DDR, SDMMC2, VI, RSVD4, 0x3138, N, …
2274 …PINGROUP(vi_d6_pl4, DDR, SDMMC2, VI, RSVD4, 0x313c, N, …
2275 …PINGROUP(vi_d7_pl5, DDR, SDMMC2, VI, RSVD4, 0x3140, N, …
2276 …PINGROUP(vi_d8_pl6, DDR, SDMMC2, VI, RSVD4, 0x3144, N, …
[all …]
|
| /Linux-v4.19/arch/mips/include/asm/mach-loongson64/ |
| D | loongson.h | 353 LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
355 LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)
|
