Searched refs:Clock (Results 1 – 25 of 359) sorted by relevance
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| /Linux-v4.19/drivers/clk/mediatek/ |
| D | Kconfig | 2 # MediaTek Clock Drivers
4 menu "Clock driver for MediaTek SoC"
14 bool "Clock driver for MediaTek MT2701"
22 bool "Clock driver for MediaTek MT2701 mmsys"
28 bool "Clock driver for MediaTek MT2701 imgsys"
34 bool "Clock driver for MediaTek MT2701 vdecsys"
40 bool "Clock driver for MediaTek MT2701 hifsys"
46 bool "Clock driver for MediaTek MT2701 ethsys"
52 bool "Clock driver for MediaTek MT2701 bdpsys"
58 bool "Clock driver for Mediatek MT2701 audsys"
[all …]
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| /Linux-v4.19/drivers/clk/ |
| D | Kconfig | 22 menu "Common Clock Framework"
26 tristate "Clock driver for WM831x/2x PMICs"
42 tristate "Clock driver for Maxim 77620/77686/77802 MFD"
49 tristate "Maxim 9485 Programmable Clock Generator"
52 This driver supports Maxim 9485 Programmable Audio Clock Generator
55 tristate "Clock driver for RK805/RK808/RK818"
64 tristate "Clock driver for Hi655x" if EXPERT
74 tristate "Clock driver controlled via SCMI interface"
84 tristate "Clock driver controlled via SCPI interface"
94 tristate "Clock driver for SiLabs 5351A/B/C"
[all …]
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| /Linux-v4.19/drivers/clk/qcom/ |
| D | Kconfig | 26 tristate "MSM8916 APCS Clock Controller"
31 Support for the APCS Clock Controller on msm8916 devices. The
37 tristate "RPM based Clock Controller"
50 tristate "RPM over SMD based Clock Controller"
63 tristate "RPMh Clock Driver"
72 tristate "APQ8084 Global Clock Controller"
81 tristate "APQ8084 Multimedia Clock Controller"
91 tristate "IPQ4019 Global Clock Controller"
99 tristate "IPQ806x Global Clock Controller"
107 tristate "IPQ806x LPASS Clock Controller"
[all …]
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| /Linux-v4.19/drivers/clk/hisilicon/ |
| D | Kconfig | 2 tristate "HI3516CV300 Clock Driver"
10 tristate "Hi3519 Clock Driver"
18 bool "Hi3660 Clock Driver"
25 tristate "Hi3798CV200 Clock Driver"
33 bool "Hi6220 Clock Driver"
47 bool "Hi6220 Stub Clock Driver" if EXPERT
55 bool "Hi3660 Stub Clock Driver" if EXPERT
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| /Linux-v4.19/Documentation/devicetree/bindings/clock/ |
| D | mvebu-gated-clock.txt | 1 * Gated Clock bindings for Marvell EBU SoCs
11 ID Clock Peripheral
14 1 pex0_en PCIe 0 Clock out
15 2 pex1_en PCIe 1 Clock out
28 ID Clock Peripheral
33 5 pex0 PCIe 0 Clock out
34 6 pex1 PCIe 1 Clock out
55 ID Clock Peripheral
82 ID Clock Peripheral
96 ID Clock Peripheral
[all …]
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| D | renesas,r8a7778-cpg-clocks.txt | 1 * Renesas R8A7778 Clock Pulse Generator (CPG)
5 The CPG also provides a Clock Domain for SoC devices, in combination with the
17 SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
39 - CPG/MSTP Clock Domain member device node:
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| D | renesas,r8a7779-cpg-clocks.txt | 1 * Renesas R8A7779 Clock Pulse Generator (CPG)
5 The CPG also provides a Clock Domain for SoC devices, in combination with the
19 SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
41 - CPG/MSTP Clock Domain member device node:
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| D | emev2-clock.txt | 1 Device tree Clock bindings for Renesas EMMA Mobile EV2
15 "Serial clock generator" in fig."Clock System Overview" of the manual,
27 Clock gating node shown as "Clock stop processing block" in the
28 fig."Clock System Overview" of the manual.
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| D | renesas,rz-cpg-clocks.txt | 1 * Renesas RZ/A1 Clock Pulse Generator (CPG)
5 The CPG also provides a Clock Domain for SoC devices, in combination with the
21 SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
43 - CPG/MSTP Clock Domain member device node:
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| D | dove-divider-clock.txt | 9 ID Clock
18 - reg : shall be the register address of the Core PLL and Clock Divider
20 Core PLL and Clock Divider Control 1 register. Thus, it will have
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| D | renesas,rcar-gen2-cpg-clocks.txt | 1 * Renesas R-Car Gen2 Clock Pulse Generator (CPG)
5 The CPG also provides a Clock Domain for SoC devices, in combination with the
28 SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
52 - CPG/MSTP Clock Domain member device node:
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| D | mvebu-core-clock.txt | 1 * Core Clock bindings for Marvell MVEBU SoCs
30 3 = hclk (SDRAM Controller Internal Clock)
31 4 = dclk (SDRAM Interface Clock)
32 5 = refclk (Reference Clock)
38 3 = mpll (MPLL Clock)
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| D | armada3700-periph-clock.txt | 1 * Peripheral Clock bindings for Marvell Armada 37xx SoCs
13 ID Clock name Description
34 ID Clock name Description
55 - reg : must be the register address of North/South Bridge Clock register
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| D | cs2000-cp.txt | 1 CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier
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| D | efm32-clock.txt | 1 * Clock bindings for Energy Micro efm32 Giant Gecko's Clock Management Unit
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| D | zynq-7000.txt | 1 Device Tree Clock bindings for the Zynq 7000 EPP
9 == Clock Controller ==
31 Clock inputs:
40 Clock outputs:
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| D | actions,owl-cmu.txt | 1 * Actions Semi Owl Clock Management Unit (CMU)
3 The Actions Semi Owl Clock Management Unit generates and supplies clock
32 Example: Clock Management Unit node:
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| D | renesas,cpg-mssr.txt | 1 * Renesas Clock Pulse Generator / Module Standby and Software Reset
3 On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
10 1. Module Standby, providing a Clock Domain to control the clock supply
53 - SoC devices that are part of the CPG/MSSR Clock Domain and can be
80 - CPG/MSSR Clock Domain member device node:
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| /Linux-v4.19/drivers/iio/frequency/ |
| D | Kconfig | 4 # Clock Distribution device drivers
11 menu "Clock Generator/Distribution"
14 tristate "Analog Devices AD9523 Low Jitter Clock Generator"
18 Clock Generator. The driver provides direct access via sysfs.
|
| /Linux-v4.19/drivers/clk/versatile/ |
| D | Kconfig | 5 bool "Clock driver for ARM Reference designs"
17 bool "Clock driver for ARM SP810 System Controller"
25 bool "Clock driver for Versatile Express OSC clock generators"
|
| /Linux-v4.19/Documentation/input/devices/ |
| D | amijoy.rst | 129 | 0 | M0H | JOY0DAT Horizontal Clock |
131 | 1 | M0HQ | JOY0DAT Horizontal Clock (quadrature) |
133 | 2 | M0V | JOY0DAT Vertical Clock |
135 | 3 | M0VQ | JOY0DAT Vertical Clock (quadrature) |
137 | 4 | M1V | JOY1DAT Horizontal Clock |
139 | 5 | M1VQ | JOY1DAT Horizontal Clock (quadrature) |
141 | 6 | M1V | JOY1DAT Vertical Clock |
143 | 7 | M1VQ | JOY1DAT Vertical Clock (quadrature) |
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| /Linux-v4.19/Documentation/devicetree/bindings/arm/altera/ |
| D | socfpga-clk-manager.txt | 1 Altera SOCFPGA Clock Manager
5 - reg : Should contain base address and length for Clock Manager
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| /Linux-v4.19/Documentation/devicetree/bindings/rtc/ |
| D | pcf8563.txt | 1 * Philips PCF8563/Epson RTC8564 Real Time Clock
3 Philips PCF8563/Epson RTC8564 Real Time Clock
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| D | xgene-rtc.txt | 1 * APM X-Gene Real Time Clock
3 RTC controller for the APM X-Gene Real Time Clock
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| /Linux-v4.19/Documentation/ABI/testing/ |
| D | sysfs-class-rtc-rtc0-device-rtc_calibration | 5 Description: Attribute for calibrating ST-Ericsson AB8500 Real Time Clock
7 calibrate the AB8500.s 32KHz Real Time Clock.
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