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Searched refs:CTR (Results 1 – 15 of 15) sorted by relevance

/Linux-v4.19/arch/x86/crypto/
Daesni-intel_avx-x86_64.S397 .macro INITIAL_BLOCKS_AVX num_initial_blocks T1 T2 T3 T4 T5 CTR XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 …
470 vmovdqu (%rax), \CTR # CTR = Y0
471 vpshufb SHUF_MASK(%rip), \CTR, \CTR
477 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
478 vmovdqa \CTR, reg_i
556 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
557 vmovdqa \CTR, \XMM1
560 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
561 vmovdqa \CTR, \XMM2
564 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
[all …]
Daesni-intel_asm.S151 #define CTR %xmm11 macro
2614 movaps IV, CTR
2615 PSHUFB_XMM BSWAP_MASK CTR
2618 MOVQ_R64_XMM CTR TCTR_LOW
2639 paddq INC, CTR
2643 paddq INC, CTR
2646 movaps CTR, IV
2726 pshufd $0x13, IV, CTR; \
2728 psrad $31, CTR; \
2729 pand GF128MUL_MASK, CTR; \
[all …]
/Linux-v4.19/tools/perf/arch/powerpc/tests/
Dregs_load.S38 #define CTR 35 * 8 macro
90 std 4, CTR(3)
/Linux-v4.19/arch/arm64/crypto/
DKconfig93 tristate "AES in ECB/CBC/CTR/XTS modes using ARMv8 Crypto Extensions"
101 tristate "AES in ECB/CBC/CTR/XTS modes using NEON instructions"
115 tristate "AES in ECB/CBC/CTR/XTS modes using bit-sliced NEON algorithm"
/Linux-v4.19/arch/arm/crypto/
DKconfig80 CTR and XTS modes
82 Bit sliced AES gives around 45% speedup on Cortex-A15 for CTR mode
94 Use an implementation of AES in CBC, CTR and XTS modes that uses
/Linux-v4.19/Documentation/crypto/
Darchitecture.rst288 the AES-NI implementation, the CTR mode, the GHASH implementation and
359 During instantiation of the GCM handle, the CTR(AES) and GHASH
360 ciphers are instantiated. The cipher handles for CTR(AES) and GHASH
363 The GCM implementation is responsible to invoke the CTR mode AES and
368 with the instantiated CTR(AES) cipher handle.
370 During instantiation of the CTR(AES) cipher, the CIPHER type
374 That means that the SKCIPHER implementation of CTR(AES) only
375 implements the CTR block chaining mode. After performing the block
378 4. The SKCIPHER of CTR(AES) now invokes the CIPHER API with the AES
/Linux-v4.19/drivers/crypto/ux500/
DKconfig15 AES-ECB, CBC and CTR with keys sizes of 128, 192 and 256 bit sizes.
/Linux-v4.19/drivers/spi/
Dspi-sh-msiof.c76 #define CTR 0x28 /* Control Register */ macro
227 data = sh_msiof_read(p, CTR); in sh_msiof_modify_ctr_wait()
230 sh_msiof_write(p, CTR, data); in sh_msiof_modify_ctr_wait()
233 if ((sh_msiof_read(p, CTR) & mask) == set) in sh_msiof_modify_ctr_wait()
380 sh_msiof_write(p, CTR, tmp); in sh_msiof_spi_set_pin_regs()
/Linux-v4.19/arch/powerpc/platforms/8xx/
DKconfig129 (by not placing conditional branches or branches to LR or CTR
/Linux-v4.19/drivers/platform/x86/
Dintel_telemetry_debugfs.c87 #define TELEM_CHECK_AND_PARSE_CTRS(EVTID, CTR) { \ argument
89 (CTR) = evtlog[index].telem_evtlog; \
Dsony-laptop.c725 SNC_HANDLE(CTR, snc_CTR_get, snc_CTR_set, NULL, 1),
/Linux-v4.19/crypto/
DKconfig401 xoring it with a salt. This algorithm is mainly useful for CTR
433 tristate "CTR support"
438 CTR: Counter mode
1051 and GCM drivers, and other CTR or CMAC/XCBC based modes that rely
1137 acceleration for CTR.
1172 for popular block cipher modes ECB, CBC, CTR and XTS is supported.
1813 bool "Enable CTR DRBG"
1817 Enable the CTR DRBG variant as defined in NIST SP800-90A.
/Linux-v4.19/drivers/crypto/
DKconfig147 As of z196 the CTR mode is hardware accelerated.
162 As of z196 the CTR mode is hardware accelerated for all AES
/Linux-v4.19/Documentation/powerpc/
Dtransactional_memory.txt62 Checkpointed registers include all GPRs, FPRs, VRs/VSRs, LR, CCR/CR, CTR, FPCSR
/Linux-v4.19/arch/arm/kvm/
Dcoproc.c812 FUNCTION_FOR32(0, 0, 0, 1, CTR)