| /Linux-v4.19/include/dt-bindings/clock/ |
| D | exynos5410.h | 40 #define CLK_UART1 258 macro
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| D | actions,s700-cmu.h | 59 #define CLK_UART1 37 macro
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| D | actions,s900-cmu.h | 86 #define CLK_UART1 68 macro
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| D | pistachio-clk.h | 43 #define CLK_UART1 49 macro
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| D | exynos5250.h | 96 #define CLK_UART1 290 macro
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| D | s5pv210.h | 163 #define CLK_UART1 142 macro
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| D | exynos5420.h | 69 #define CLK_UART1 258 macro
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| D | exynos4.h | 154 #define CLK_UART1 313 macro
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| D | exynos3250.h | 224 #define CLK_UART1 215 macro
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| D | sprd,sc9860-clk.h | 86 #define CLK_UART1 3 macro
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| /Linux-v4.19/drivers/clk/zte/ |
| D | clk-zx296702.c | 50 #define CLK_UART1 (lsp1crpm_base + 0x24) macro
702 ARRAY_SIZE(uart_wclk_sel), CLK_UART1, 4, 1); in zx296702_lsp1_clocks_init()
704 zx_gate("uart1_wclk", "uart1_wclk_mux", CLK_UART1, 1); in zx296702_lsp1_clocks_init()
706 zx_gate("uart1_pclk", "lsp1_apb_pclk", CLK_UART1, 0); in zx296702_lsp1_clocks_init()
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| /Linux-v4.19/drivers/clk/samsung/ |
| D | clk-exynos5410.c | 201 GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
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| D | clk-s5pv210.c | 616 GATE(CLK_UART1, "uart1", "dout_pclkp", CLK_GATE_IP3, 18, 0, 0),
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| D | clk-exynos5250.c | 615 GATE(CLK_UART1, "uart1", "div_aclk66", GATE_IP_PERIC, 1, 0, 0),
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| D | clk-exynos3250.c | 667 GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
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| D | clk-exynos4.c | 995 GATE(CLK_UART1, "uart1", "aclk100", GATE_IP_PERIL, 1,
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| D | clk-exynos5420.c | 1089 GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric",
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| /Linux-v4.19/drivers/clk/pistachio/ |
| D | clk-pistachio.c | 39 GATE(CLK_UART1, "uart1", "uart1_div", 0x104, 17),
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| /Linux-v4.19/arch/arm/boot/dts/ |
| D | s5pv210.dtsi | 347 clocks = <&clocks CLK_UART1>, <&clocks CLK_UART1>,
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| D | exynos5410.dtsi | 353 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
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| D | exynos3250.dtsi | 494 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
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| /Linux-v4.19/drivers/clk/actions/ |
| D | owl-s700.c | 524 [CLK_UART1] = &clk_uart1.common.hw,
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| D | owl-s900.c | 675 [CLK_UART1] = &uart1_clk.common.hw,
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| /Linux-v4.19/drivers/clk/renesas/ |
| D | r9a06g032-clocks.c | 294 D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 1, 0x1b6, 0x1b7, 0x1b8, 0x1b9),
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| /Linux-v4.19/arch/mips/boot/dts/img/ |
| D | pistachio.dtsi | 275 clocks = <&clk_core CLK_UART1>, <&cr_periph SYS_CLK_UART1>;
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