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Searched refs:CLK_UART0 (Results 1 – 25 of 31) sorted by relevance

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/Linux-v4.19/include/dt-bindings/clock/
Dexynos5410.h39 #define CLK_UART0 257 macro
Dactions,s700-cmu.h58 #define CLK_UART0 36 macro
Dactions,s900-cmu.h85 #define CLK_UART0 67 macro
Dpistachio-clk.h42 #define CLK_UART0 48 macro
Dexynos5250.h95 #define CLK_UART0 289 macro
Ds5pv210.h164 #define CLK_UART0 143 macro
Dexynos5420.h68 #define CLK_UART0 257 macro
Dexynos4.h153 #define CLK_UART0 312 macro
Dexynos3250.h225 #define CLK_UART0 216 macro
Dsprd,sc9860-clk.h85 #define CLK_UART0 2 macro
/Linux-v4.19/drivers/clk/zte/
Dclk-zx296702.c49 #define CLK_UART0 (lsp1crpm_base + 0x20) macro
691 ARRAY_SIZE(uart_wclk_sel), CLK_UART0, 4, 1); in zx296702_lsp1_clocks_init()
695 zx_gate("uart0_wclk", "uart0_wclk_mux", CLK_UART0, 31); in zx296702_lsp1_clocks_init()
697 zx_gate("uart0_pclk", "lsp1_apb_pclk", CLK_UART0, 0); in zx296702_lsp1_clocks_init()
/Linux-v4.19/Documentation/devicetree/bindings/clock/
Dexynos5410-clock.txt48 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
Dexynos3250-clock.txt55 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
/Linux-v4.19/drivers/clk/samsung/
Dclk-exynos5410.c200 GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
Dclk-s5pv210.c617 GATE(CLK_UART0, "uart0", "dout_pclkp", CLK_GATE_IP3, 17, 0, 0),
Dclk-exynos5250.c614 GATE(CLK_UART0, "uart0", "div_aclk66", GATE_IP_PERIC, 0, 0, 0),
Dclk-exynos3250.c668 GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
/Linux-v4.19/drivers/clk/pistachio/
Dclk-pistachio.c38 GATE(CLK_UART0, "uart0", "uart0_div", 0x104, 16),
/Linux-v4.19/arch/arm/boot/dts/
Ds5pv210.dtsi335 clocks = <&clocks CLK_UART0>, <&clocks CLK_UART0>,
Dexynos5410.dtsi346 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
Dexynos3250.dtsi483 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
/Linux-v4.19/drivers/clk/actions/
Dowl-s700.c523 [CLK_UART0] = &clk_uart0.common.hw,
Dowl-s900.c674 [CLK_UART0] = &uart0_clk.common.hw,
/Linux-v4.19/drivers/clk/renesas/
Dr9a06g032-clocks.c293 D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5),
/Linux-v4.19/arch/mips/boot/dts/img/
Dpistachio.dtsi260 clocks = <&clk_core CLK_UART0>, <&cr_periph SYS_CLK_UART0>;

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