Searched refs:CLK_TOP_UNIVPLL2_D4 (Results 1 – 13 of 13) sorted by relevance
| /Linux-v4.19/include/dt-bindings/clock/ |
| D | mt8135-clk.h | 57 #define CLK_TOP_UNIVPLL2_D4 38 macro
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| D | mt7622-clk.h | 57 #define CLK_TOP_UNIVPLL2_D4 37 macro
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| D | mt6797-clk.h | 81 #define CLK_TOP_UNIVPLL2_D4 63 macro
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| D | mt8173-clk.h | 86 #define CLK_TOP_UNIVPLL2_D4 68 macro
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| D | mt2712-clk.h | 70 #define CLK_TOP_UNIVPLL2_D4 31 macro
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| D | mt2701-clk.h | 48 #define CLK_TOP_UNIVPLL2_D4 30 macro
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| /Linux-v4.19/Documentation/devicetree/bindings/spi/ |
| D | spi-mt65xx.txt | 26 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
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| /Linux-v4.19/drivers/clk/mediatek/ |
| D | clk-mt8135.c | 76 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_416m", 1, 4),
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| D | clk-mt6797.c | 62 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 4),
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| D | clk-mt7622.c | 423 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
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| D | clk-mt2701.c | 97 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4),
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| D | clk-mt2712.c | 116 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1,
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| D | clk-mt8173.c | 121 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4),
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