Searched refs:CLK_TOP_UNIVPLL1_D8 (Results 1 – 13 of 13) sorted by relevance
| /Linux-v4.19/include/dt-bindings/clock/ |
| D | mt8135-clk.h | 54 #define CLK_TOP_UNIVPLL1_D8 35 macro
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| D | mt7622-clk.h | 54 #define CLK_TOP_UNIVPLL1_D8 34 macro
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| D | mt6797-clk.h | 78 #define CLK_TOP_UNIVPLL1_D8 60 macro
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| D | mt8173-clk.h | 83 #define CLK_TOP_UNIVPLL1_D8 65 macro
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| D | mt2712-clk.h | 67 #define CLK_TOP_UNIVPLL1_D8 28 macro
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| D | mt2701-clk.h | 46 #define CLK_TOP_UNIVPLL1_D8 28 macro
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| /Linux-v4.19/Documentation/devicetree/bindings/spi/ |
| D | spi-mt65xx.txt | 27 - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
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| /Linux-v4.19/drivers/clk/mediatek/ |
| D | clk-mt8135.c | 72 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8),
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| D | clk-mt6797.c | 59 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8),
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| D | clk-mt7622.c | 420 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16),
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| D | clk-mt2701.c | 94 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8),
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| D | clk-mt2712.c | 110 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1,
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| D | clk-mt8173.c | 118 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univ_624m", 1, 8),
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