Searched refs:CLK_TOP_SYSPLL4_D2 (Results 1 – 11 of 11) sorted by relevance
| /Linux-v4.19/include/dt-bindings/clock/ |
| D | mt7622-clk.h | 47 #define CLK_TOP_SYSPLL4_D2 27 macro
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| D | mt6797-clk.h | 68 #define CLK_TOP_SYSPLL4_D2 50 macro
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| D | mt8173-clk.h | 73 #define CLK_TOP_SYSPLL4_D2 55 macro
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| D | mt2712-clk.h | 56 #define CLK_TOP_SYSPLL4_D2 17 macro
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| D | mt2701-clk.h | 33 #define CLK_TOP_SYSPLL4_D2 15 macro
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| /Linux-v4.19/Documentation/devicetree/bindings/spi/ |
| D | spi-mt65xx.txt | 25 - <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ.
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| /Linux-v4.19/drivers/clk/mediatek/ |
| D | clk-mt6797.c | 49 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
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| D | clk-mt7622.c | 413 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
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| D | clk-mt2701.c | 80 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
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| D | clk-mt2712.c | 88 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1,
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| D | clk-mt8173.c | 106 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2),
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