Searched refs:CLK_TOP_SYSPLL3_D2 (Results 1 – 15 of 15) sorted by relevance
| /Linux-v4.19/Documentation/devicetree/bindings/spi/ |
| D | spi-mt65xx.txt | 23 - <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ.
54 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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| /Linux-v4.19/include/dt-bindings/clock/ |
| D | mt7622-clk.h | 45 #define CLK_TOP_SYSPLL3_D2 25 macro
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| D | mt6797-clk.h | 65 #define CLK_TOP_SYSPLL3_D2 47 macro
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| D | mt8173-clk.h | 70 #define CLK_TOP_SYSPLL3_D2 52 macro
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| D | mt2712-clk.h | 53 #define CLK_TOP_SYSPLL3_D2 14 macro
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| D | mt2701-clk.h | 31 #define CLK_TOP_SYSPLL3_D2 13 macro
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| /Linux-v4.19/arch/arm/boot/dts/ |
| D | mt2701.dtsi | 342 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
402 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
415 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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| D | mt7623.dtsi | 469 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
548 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
562 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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| /Linux-v4.19/drivers/clk/mediatek/ |
| D | clk-mt6797.c | 46 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
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| D | clk-mt7622.c | 411 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
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| D | clk-mt2701.c | 78 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
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| D | clk-mt2712.c | 82 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1,
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| D | clk-mt8173.c | 103 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2),
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| /Linux-v4.19/arch/arm64/boot/dts/mediatek/ |
| D | mt7622.dtsi | 443 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
518 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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| D | mt8173.dtsi | 659 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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