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/Linux-v4.19/arch/arc/include/asm/
Dperf_event.h126 #define C(_x) PERF_COUNT_HW_CACHE_##_x macro
129 static const unsigned arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
130 [C(L1D)] = {
131 [C(OP_READ)] = {
132 [C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC,
133 [C(RESULT_MISS)] = PERF_COUNT_ARC_DCLM,
135 [C(OP_WRITE)] = {
136 [C(RESULT_ACCESS)] = PERF_COUNT_ARC_STC,
137 [C(RESULT_MISS)] = PERF_COUNT_ARC_DCSM,
139 [C(OP_PREFETCH)] = {
[all …]
/Linux-v4.19/arch/sh/kernel/cpu/sh4/
Dperf_event.c87 #define C(x) PERF_COUNT_HW_CACHE_##x macro
94 [ C(L1D) ] = {
95 [ C(OP_READ) ] = {
96 [ C(RESULT_ACCESS) ] = 0x0001,
97 [ C(RESULT_MISS) ] = 0x0004,
99 [ C(OP_WRITE) ] = {
100 [ C(RESULT_ACCESS) ] = 0x0002,
101 [ C(RESULT_MISS) ] = 0x0005,
103 [ C(OP_PREFETCH) ] = {
104 [ C(RESULT_ACCESS) ] = 0,
[all …]
/Linux-v4.19/arch/sh/kernel/cpu/sh4a/
Dperf_event.c112 #define C(x) PERF_COUNT_HW_CACHE_##x macro
119 [ C(L1D) ] = {
120 [ C(OP_READ) ] = {
121 [ C(RESULT_ACCESS) ] = 0x0031,
122 [ C(RESULT_MISS) ] = 0x0032,
124 [ C(OP_WRITE) ] = {
125 [ C(RESULT_ACCESS) ] = 0x0039,
126 [ C(RESULT_MISS) ] = 0x003a,
128 [ C(OP_PREFETCH) ] = {
129 [ C(RESULT_ACCESS) ] = 0,
[all …]
/Linux-v4.19/arch/x86/events/intel/
Dcore.c389 [ C(L1D ) ] = {
390 [ C(OP_READ) ] = {
391 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
392 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
394 [ C(OP_WRITE) ] = {
395 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
396 [ C(RESULT_MISS) ] = 0x0,
398 [ C(OP_PREFETCH) ] = {
399 [ C(RESULT_ACCESS) ] = 0x0,
400 [ C(RESULT_MISS) ] = 0x0,
[all …]
Dp6.c28 [ C(L1D) ] = {
29 [ C(OP_READ) ] = {
30 [ C(RESULT_ACCESS) ] = 0x0043, /* DATA_MEM_REFS */
31 [ C(RESULT_MISS) ] = 0x0045, /* DCU_LINES_IN */
33 [ C(OP_WRITE) ] = {
34 [ C(RESULT_ACCESS) ] = 0,
35 [ C(RESULT_MISS) ] = 0x0f29, /* L2_LD:M:E:S:I */
37 [ C(OP_PREFETCH) ] = {
38 [ C(RESULT_ACCESS) ] = 0,
39 [ C(RESULT_MISS) ] = 0,
[all …]
Dknc.c26 [ C(L1D) ] = {
27 [ C(OP_READ) ] = {
32 [ C(RESULT_ACCESS) ] = ARCH_PERFMON_EVENTSEL_INT,
34 [ C(RESULT_MISS) ] = 0x0003, /* DATA_READ_MISS */
36 [ C(OP_WRITE) ] = {
37 [ C(RESULT_ACCESS) ] = 0x0001, /* DATA_WRITE */
38 [ C(RESULT_MISS) ] = 0x0004, /* DATA_WRITE_MISS */
40 [ C(OP_PREFETCH) ] = {
41 [ C(RESULT_ACCESS) ] = 0x0011, /* L1_DATA_PF1 */
42 [ C(RESULT_MISS) ] = 0x001c, /* L1_DATA_PF1_MISS */
[all …]
/Linux-v4.19/arch/arm/kernel/
Dperf_event_v7.c179 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
180 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
181 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
182 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
184 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
185 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
187 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
188 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
189 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
190 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
[all …]
Dperf_event_v6.c96 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
97 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
98 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
99 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
101 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS,
109 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS,
110 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS,
112 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS,
113 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS,
159 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS,
[all …]
/Linux-v4.19/lib/
Dsha1.c55 #define SHA_ROUND(t, input, fn, constant, A, B, C, D, E) do { \ argument
60 #define T_0_15(t, A, B, C, D, E) SHA_ROUND(t, SHA_SRC, (((C^D)&B)^D) , 0x5a827999, A, B, C, D, E ) argument
61 #define T_16_19(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, (((C^D)&B)^D) , 0x5a827999, A, B, C, D, E ) argument
62 #define T_20_39(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, (B^C^D) , 0x6ed9eba1, A, B, C, D, E ) argument
63 #define T_40_59(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, ((B&C)+(D&(B^C))) , 0x8f1bbcdc, A, B, C, D,… argument
64 #define T_60_79(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, (B^C^D) , 0xca62c1d6, A, B, C, D, E ) argument
84 __u32 A, B, C, D, E; in sha_transform() local
88 C = digest[2]; in sha_transform()
93 T_0_15( 0, A, B, C, D, E); in sha_transform()
94 T_0_15( 1, E, A, B, C, D); in sha_transform()
[all …]
/Linux-v4.19/arch/powerpc/perf/
Dpower8-pmu.c250 #define C(x) PERF_COUNT_HW_CACHE_##x macro
257 static int power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
258 [ C(L1D) ] = {
259 [ C(OP_READ) ] = {
260 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
261 [ C(RESULT_MISS) ] = PM_LD_MISS_L1,
263 [ C(OP_WRITE) ] = {
264 [ C(RESULT_ACCESS) ] = 0,
265 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
267 [ C(OP_PREFETCH) ] = {
[all …]
Dpower9-pmu.c315 #define C(x) PERF_COUNT_HW_CACHE_##x macro
322 static int power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
323 [ C(L1D) ] = {
324 [ C(OP_READ) ] = {
325 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
326 [ C(RESULT_MISS) ] = PM_LD_MISS_L1_FIN,
328 [ C(OP_WRITE) ] = {
329 [ C(RESULT_ACCESS) ] = 0,
330 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
332 [ C(OP_PREFETCH) ] = {
[all …]
De6500-pmu.c32 #define C(x) PERF_COUNT_HW_CACHE_##x macro
39 static int e6500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
40 [C(L1D)] = {
42 [C(OP_READ)] = { 27, 222 },
43 [C(OP_WRITE)] = { 28, 223 },
44 [C(OP_PREFETCH)] = { 29, 0 },
46 [C(L1I)] = {
48 [C(OP_READ)] = { 2, 254 },
49 [C(OP_WRITE)] = { -1, -1 },
50 [C(OP_PREFETCH)] = { 37, 0 },
[all …]
De500-pmu.c31 #define C(x) PERF_COUNT_HW_CACHE_##x macro
38 static int e500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
43 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
44 [C(OP_READ)] = { 27, 0 },
45 [C(OP_WRITE)] = { 28, 0 },
46 [C(OP_PREFETCH)] = { 29, 0 },
48 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
49 [C(OP_READ)] = { 2, 60 },
50 [C(OP_WRITE)] = { -1, -1 },
51 [C(OP_PREFETCH)] = { 0, 0 },
[all …]
Dmpc7450-pmu.c354 #define C(x) PERF_COUNT_HW_CACHE_##x macro
361 static int mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
362 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
363 [C(OP_READ)] = { 0, 0x225 },
364 [C(OP_WRITE)] = { 0, 0x227 },
365 [C(OP_PREFETCH)] = { 0, 0 },
367 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
368 [C(OP_READ)] = { 0x129, 0x115 },
369 [C(OP_WRITE)] = { -1, -1 },
370 [C(OP_PREFETCH)] = { 0x634, 0 },
[all …]
Dpower6-pmu.c480 #define C(x) PERF_COUNT_HW_CACHE_##x macro
488 static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
489 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
490 [C(OP_READ)] = { 0x280030, 0x80080 },
491 [C(OP_WRITE)] = { 0x180032, 0x80088 },
492 [C(OP_PREFETCH)] = { 0x810a4, 0 },
494 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
495 [C(OP_READ)] = { 0, 0x100056 },
496 [C(OP_WRITE)] = { -1, -1 },
497 [C(OP_PREFETCH)] = { 0x4008c, 0 },
[all …]
Dpower7-pmu.c331 #define C(x) PERF_COUNT_HW_CACHE_##x macro
338 static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
339 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
340 [C(OP_READ)] = { 0xc880, 0x400f0 },
341 [C(OP_WRITE)] = { 0, 0x300f0 },
342 [C(OP_PREFETCH)] = { 0xd8b8, 0 },
344 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
345 [C(OP_READ)] = { 0, 0x200fc },
346 [C(OP_WRITE)] = { -1, -1 },
347 [C(OP_PREFETCH)] = { 0x408a, 0 },
[all …]
Dppc970-pmu.c432 #define C(x) PERF_COUNT_HW_CACHE_##x macro
439 static int ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
440 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
441 [C(OP_READ)] = { 0x8810, 0x3810 },
442 [C(OP_WRITE)] = { 0x7810, 0x813 },
443 [C(OP_PREFETCH)] = { 0x731, 0 },
445 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
446 [C(OP_READ)] = { 0, 0 },
447 [C(OP_WRITE)] = { -1, -1 },
448 [C(OP_PREFETCH)] = { 0, 0 },
[all …]
/Linux-v4.19/arch/sparc/kernel/
Dperf_event.c147 #define C(x) PERF_COUNT_HW_CACHE_##x macro
221 [C(L1D)] = {
222 [C(OP_READ)] = {
223 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
224 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
226 [C(OP_WRITE)] = {
227 [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER },
228 [C(RESULT_MISS)] = { 0x0a, PIC_UPPER },
230 [C(OP_PREFETCH)] = {
231 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
[all …]
/Linux-v4.19/arch/mips/kernel/
Dperf_event_mipsxx.c83 #define C(x) PERF_COUNT_HW_CACHE_##x macro
889 [C(L1D)] = {
896 [C(OP_READ)] = {
897 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
898 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
900 [C(OP_WRITE)] = {
901 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
902 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
905 [C(L1I)] = {
906 [C(OP_READ)] = {
[all …]
/Linux-v4.19/arch/riscv/kernel/
Dperf_event.c52 #define C(x) PERF_COUNT_HW_CACHE_##x macro
56 [C(L1D)] = {
57 [C(OP_READ)] = {
58 [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
59 [C(RESULT_MISS)] = RISCV_OP_UNSUPP,
61 [C(OP_WRITE)] = {
62 [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
63 [C(RESULT_MISS)] = RISCV_OP_UNSUPP,
65 [C(OP_PREFETCH)] = {
66 [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
[all …]
/Linux-v4.19/arch/x86/events/amd/
Dcore.c15 [ C(L1D) ] = {
16 [ C(OP_READ) ] = {
17 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
18 [ C(RESULT_MISS) ] = 0x0141, /* Data Cache Misses */
20 [ C(OP_WRITE) ] = {
21 [ C(RESULT_ACCESS) ] = 0,
22 [ C(RESULT_MISS) ] = 0,
24 [ C(OP_PREFETCH) ] = {
25 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */
26 [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */
[all …]
/Linux-v4.19/arch/arm64/kernel/
Dperf_event.c211 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
212 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
213 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
214 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
216 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
217 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
219 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
220 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB,
222 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
223 [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
[all …]
/Linux-v4.19/drivers/scsi/isci/
Drequest.h228 C(REQ_INIT),\
229 C(REQ_CONSTRUCTED),\
230 C(REQ_STARTED),\
231 C(REQ_STP_UDMA_WAIT_TC_COMP),\
232 C(REQ_STP_UDMA_WAIT_D2H),\
233 C(REQ_STP_NON_DATA_WAIT_H2D),\
234 C(REQ_STP_NON_DATA_WAIT_D2H),\
235 C(REQ_STP_PIO_WAIT_H2D),\
236 C(REQ_STP_PIO_WAIT_FRAME),\
237 C(REQ_STP_PIO_DATA_IN),\
[all …]
Dphy.h377 C(PHY_INITIAL),\
378 C(PHY_STOPPED),\
379 C(PHY_STARTING),\
380 C(PHY_SUB_INITIAL),\
381 C(PHY_SUB_AWAIT_OSSP_EN),\
382 C(PHY_SUB_AWAIT_SAS_SPEED_EN),\
383 C(PHY_SUB_AWAIT_IAF_UF),\
384 C(PHY_SUB_AWAIT_SAS_POWER),\
385 C(PHY_SUB_AWAIT_SATA_POWER),\
386 C(PHY_SUB_AWAIT_SATA_PHY_EN),\
[all …]
Dremote_device.h266 C(DEV_INITIAL),\
267 C(DEV_STOPPED),\
268 C(DEV_STARTING),\
269 C(DEV_READY),\
270 C(STP_DEV_IDLE),\
271 C(STP_DEV_CMD),\
272 C(STP_DEV_NCQ),\
273 C(STP_DEV_NCQ_ERROR),\
274 C(STP_DEV_ATAPI_ERROR),\
275 C(STP_DEV_AWAIT_RESET),\
[all …]

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