Searched refs:AVIVO_D1CRTC_CONTROL (Results 1 – 5 of 5) sorted by relevance
305 crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN; in rv515_mc_stop()308 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); in rv515_mc_stop()313 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); in rv515_mc_stop()326 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); in rv515_mc_stop()328 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); in rv515_mc_stop()447 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); in rv515_mc_resume()449 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); in rv515_mc_resume()
92 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) in avivo_wait_for_vblank()322 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); in rs600_pm_prepare()324 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in rs600_pm_prepare()340 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); in rs600_pm_finish()342 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in rs600_pm_finish()
348 #define AVIVO_D1CRTC_CONTROL 0x6080 macro
681 reg = RREG32(AVIVO_D1CRTC_CONTROL) | in radeon_card_posted()
1588 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { in r600_is_display_hung()
