Searched refs:APBC_UART0 (Results 1 – 7 of 7) sorted by relevance
| /Linux-v4.19/drivers/clk/mmp/ |
| D | clk-of-pxa168.c | 28 #define APBC_UART0 0x0 macro
131 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0…
153 …{PXA168_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &u…
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| D | clk-of-pxa910.c | 28 #define APBC_UART0 0x0 macro
129 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0…
151 …{PXA910_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &u…
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| D | clk-pxa910.c | 25 #define APBC_UART0 0x0 macro
207 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); in pxa910_clk_init()
212 apbc_base + APBC_UART0, 10, 0, &clk_lock); in pxa910_clk_init()
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| D | clk-of-mmp2.c | 34 #define APBC_UART0 0x2c macro
142 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0…
168 …{MMP2_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x7, 0x3, 0x0, 0, &uar…
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| D | clk-pxa168.c | 25 #define APBC_UART0 0x0 macro
202 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); in pxa168_clk_init()
207 apbc_base + APBC_UART0, 10, 0, &clk_lock); in pxa168_clk_init()
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| D | clk-mmp2.c | 31 #define APBC_UART0 0x2c macro
248 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); in mmp2_clk_init()
253 apbc_base + APBC_UART0, 10, 0, &clk_lock); in mmp2_clk_init()
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| /Linux-v4.19/arch/arm/mach-mmp/ |
| D | clock-pxa910.c | 18 #define APBC_UART0 APBC_REG(0x000) macro
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