Searched refs:APBC_PWM3 (Results 1 – 9 of 9) sorted by relevance
| /Linux-v4.19/arch/arm/mach-mmp/ |
| D | clock-pxa910.c | 23 #define APBC_PWM3 APBC_REG(0x014) macro
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| D | clock-pxa168.c | 23 #define APBC_PWM3 APBC_REG(0x014) macro
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| D | clock-mmp2.c | 31 #define APBC_PWM3 APBC_REG(0x048) macro
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| /Linux-v4.19/drivers/clk/mmp/ |
| D | clk-of-pxa168.c | 34 #define APBC_PWM3 0x18 macro
151 …{PXA168_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_…
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| D | clk-of-pxa910.c | 34 #define APBC_PWM3 0x18 macro
149 …{PXA910_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_…
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| D | clk-pxa910.c | 31 #define APBC_PWM3 0x18 macro
201 apbc_base + APBC_PWM3, 10, 0, &clk_lock); in pxa910_clk_init()
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| D | clk-of-mmp2.c | 42 #define APBC_PWM3 0x48 macro
166 …{MMP2_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x7, 0x3, 0x0, 0, &reset_lo…
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| D | clk-pxa168.c | 31 #define APBC_PWM3 0x18 macro
196 apbc_base + APBC_PWM3, 10, 0, &clk_lock); in pxa168_clk_init()
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| D | clk-mmp2.c | 39 #define APBC_PWM3 0x48 macro
242 apbc_base + APBC_PWM3, 10, 0, &clk_lock); in mmp2_clk_init()
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