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/Linux-v6.1/Documentation/devicetree/bindings/net/
Dcdns,macb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence MACB/GEM Ethernet controller
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
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/Linux-v6.1/arch/arm64/boot/dts/xilinx/
Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/power/xlnx-zynqmp-power.h>
17 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
20 compatible = "xlnx,zynqmp";
21 #address-cells = <2>;
22 #size-cells = <2>;
25 #address-cells = <1>;
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/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dxlnx,zynqmp-clk.txt1 --------------------------------------------------------------------------
4 --------------------------------------------------------------------------
12 - #clock-cells: Must be 1
13 - compatible: Must contain: "xlnx,zynqmp-clk"
14 - clocks: List of clock specifiers which are external input
18 - clock-names: List of clock names which are exteral input clocks
22 Input clocks for zynqmp Ultrascale+ clock controller:
26 - pss_ref_clk (PS reference clock)
27 - video_clk (reference clock for video system )
28 - pss_alt_ref_clk (alternative PS reference clock)
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/Linux-v6.1/drivers/firmware/xilinx/
Dzynqmp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2022 Xilinx, Inc.
13 #include <linux/arm-smccc.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
26 #include <linux/firmware/xlnx-event-manager.h>
27 #include "zynqmp-debug.h"
34 /* BOOT_PIN_CTRL- Used to control the mode pins after boot */
36 /* BOOT_PIN_CTRL_MASK- out_val[11:8], out_en[3:0] */
53 * struct zynqmp_devinfo - Structure for Zynqmp device instance
63 * struct pm_api_feature_data - PM API Feature data
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/Linux-v6.1/drivers/net/ethernet/cadence/
Dmacb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2004-2006 Atmel Corporation
80 /* GEM register offsets. */
86 #define GEM_HS_MAC_CONFIG 0x0050 /* GEM high speed config */
110 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
111 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
112 #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
113 #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
114 #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
131 #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
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Dmacb_main.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cadence MACB/GEM Ethernet Controller driver
5 * Copyright (C) 2004-2006 Atmel Corporation
10 #include <linux/clk-provider.h>
25 #include <linux/dma-mapping.h>
41 #include <linux/firmware/xlnx-zynqmp.h>
58 * (bp)->rx_ring_size)
64 * (bp)->tx_ring_size)
67 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
78 …MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN -…
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