Home
last modified time | relevance | path

Searched +full:zynqmp +full:- +full:firmware (Results 1 – 25 of 47) sorted by relevance

12

/Linux-v6.1/Documentation/ABI/stable/
Dsysfs-driver-firmware-zynqmp1 What: /sys/devices/platform/firmware\:zynqmp-firmware/ggs*
11 The register is reset during system or power-on
17 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
18 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
22 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
23 # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
27 What: /sys/devices/platform/firmware\:zynqmp-firmware/pggs*
38 This register is only reset by the power-on reset
46 # cat /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
47 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/firmware/xilinx/
Dxlnx,zynqmp-firmware.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx firmware driver
10 - Nava kishore Manne <nava.manne@xilinx.com>
12 description: The zynqmp-firmware node describes the interface to platform
13 firmware. ZynqMP has an interface to communicate with secure firmware.
14 Firmware driver provides an interface to firmware APIs. Interface APIs
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/power/reset/
Dxlnx,zynqmp-power.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/xlnx,zynqmp-power.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@xilinx.com>
13 The zynqmp-power node describes the power management configurations.
18 const: xlnx,zynqmp-power
28 that will be the phandle to the intended sub-mailbox
34 xlnx,zynqmp-ipi-mailbox.txt for typical controller that
37 - description: tx channel
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/crypto/
Dxlnx,zynqmp-aes.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/xlnx,zynqmp-aes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP AES-GCM Hardware Accelerator
10 - Kalyani Akula <kalyani.akula@xilinx.com>
11 - Michal Simek <michal.simek@xilinx.com>
14 The ZynqMP AES-GCM hardened cryptographic accelerator is used to
19 const: xlnx,zynqmp-aes
22 - compatible
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dxlnx,zynqmp-clk.txt1 --------------------------------------------------------------------------
3 Zynq MPSoC firmware interface
4 --------------------------------------------------------------------------
12 - #clock-cells: Must be 1
13 - compatible: Must contain: "xlnx,zynqmp-clk"
14 - clocks: List of clock specifiers which are external input
18 - clock-names: List of clock names which are exteral input clocks
22 Input clocks for zynqmp Ultrascale+ clock controller:
26 - pss_ref_clk (PS reference clock)
27 - video_clk (reference clock for video system )
[all …]
Dxlnx,versal-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@xilinx.com>
11 - Jolly Shah <jolly.shah@xilinx.com>
12 - Rajan Vaja <rajan.vaja@xilinx.com>
23 const: xlnx,versal-clk
25 "#clock-cells":
32 - description: reference clock
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/fpga/
Dxlnx,zynqmp-pcap-fpga.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <navam@xilinx.com>
14 The ZynqMP SoC uses the PCAP (Processor Configuration Port) to
16 firmware interface.
20 const: xlnx,zynqmp-pcap-fpga
23 - compatible
28 - |
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/nvmem/
Dxlnx,zynqmp-nvmem.txt1 --------------------------------------------------------------------------
2 = Zynq UltraScale+ MPSoC nvmem firmware driver binding =
3 --------------------------------------------------------------------------
5 like soc revision, IDCODE... etc, By using the firmware interface.
8 - compatible: should be "xlnx,zynqmp-nvmem-fw"
14 -------
16 -------
17 firmware {
18 zynqmp_firmware: zynqmp-firmware {
19 compatible = "xlnx,zynqmp-firmware";
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/reset/
Dxlnx,zynqmp-reset.txt1 --------------------------------------------------------------------------
3 --------------------------------------------------------------------------
7 about zynqmp resets.
13 - compatible: "xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform
14 "xlnx,versal-reset" for Versal platform
15 - #reset-cells: Specifies the number of cells needed to encode reset
18 -------
20 -------
22 firmware {
23 zynqmp_firmware: zynqmp-firmware {
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/power/
Dxlnx,zynqmp-genpd.txt1 -----------------------------------------------------------
3 -----------------------------------------------------------
4 The binding for zynqmp-power-controller follow the common
7 [1] Documentation/devicetree/bindings/power/power-domain.yaml
12 - Below property should be in zynqmp-firmware node.
13 - #power-domain-cells: Number of cells in a PM domain specifier. Must be 1.
16 include/dt-bindings/power/xlnx-zynqmp-power.h.
18 -------
20 -------
22 firmware {
[all …]
/Linux-v6.1/drivers/firmware/xilinx/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 menu "Zynq MPSoC Firmware Drivers"
8 bool "Enable Xilinx Zynq MPSoC firmware interface"
13 Firmware interface driver is used by different
14 drivers to communicate with the firmware for
16 Say yes to enable ZynqMP firmware interface driver.
20 bool "Enable Xilinx Zynq MPSoC firmware debug APIs"
23 Say yes to enable ZynqMP firmware interface debug APIs.
Dzynqmp-debug.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx Zynq MPSoC Firmware layer for debugfs APIs
5 * Copyright (C) 2014-2018 Xilinx, Inc.
19 #include <linux/firmware/xlnx-zynqmp.h>
20 #include "zynqmp-debug.h"
41 * zynqmp_pm_argument_value() - Extract argument value from a PM-API request
42 * @arg: Entered PM-API argument in string format
61 * get_pm_api_id() - Extract API-ID from a PM-API request
62 * @pm_api_req: Entered PM-API argument in string format
63 * @pm_id: API-ID
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/gpio/
Dxlnx,zynqmp-gpio-modepin.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: ZynqMP Mode Pin GPIO controller
10 PS_MODE is 4-bits boot mode pins sampled on POR deassertion. Mode Pin
15 - Piyush Mehta <piyush.mehta@xilinx.com>
19 const: xlnx,zynqmp-gpio-modepin
21 gpio-controller: true
23 "#gpio-cells":
[all …]
/Linux-v6.1/Documentation/driver-api/xilinx/
Deemi.rst5 Xilinx Zynq MPSoC Firmware Interface
6 -------------------------------------
7 The zynqmp-firmware node describes the interface to platform firmware.
8 ZynqMP has an interface to communicate with secure firmware. Firmware
9 driver provides an interface to firmware APIs. Interface APIs can be
13 ----------------------------------------------
23 ------
30 - IOCTL_SET_PLL_FRAC_MODE 8
31 - IOCTL_GET_PLL_FRAC_MODE 9
32 - IOCTL_SET_PLL_FRAC_DATA 10
[all …]
/Linux-v6.1/drivers/nvmem/
Dzynqmp_nvmem.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/nvmem-provider.h>
10 #include <linux/firmware/xlnx-zynqmp.h>
30 dev_dbg(priv->dev, "Read chipid val %x %x\n", idcode, version); in zynqmp_nvmem_read()
37 .name = "zynqmp-nvmem",
45 { .compatible = "xlnx,zynqmp-nvmem-fw", },
52 struct device *dev = &pdev->dev; in zynqmp_nvmem_probe()
57 return -ENOMEM; in zynqmp_nvmem_probe()
59 priv->dev = dev; in zynqmp_nvmem_probe()
64 priv->nvmem = devm_nvmem_register(dev, &econfig); in zynqmp_nvmem_probe()
[all …]
/Linux-v6.1/arch/arm64/boot/dts/xilinx/
Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/power/xlnx-zynqmp-power.h>
17 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
20 compatible = "xlnx,zynqmp";
21 #address-cells = <2>;
22 #size-cells = <2>;
25 #address-cells = <1>;
[all …]
/Linux-v6.1/drivers/clk/zynqmp/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 bool "Support for Xilinx ZynqMP Ultrascale+ clock controllers"
8 Support for the Zynqmp Ultrascale clock controller.
9 It has a dependency on the PMU firmware.
/Linux-v6.1/drivers/fpga/
Dzynqmp-fpga.c1 // SPDX-License-Identifier: GPL-2.0+
6 #include <linux/dma-mapping.h>
7 #include <linux/fpga/fpga-mgr.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
19 * struct zynqmp_fpga_priv - Private data structure
34 priv = mgr->priv; in zynqmp_fpga_ops_write_init()
35 priv->flags = info->flags; in zynqmp_fpga_ops_write_init()
49 priv = mgr->priv; in zynqmp_fpga_ops_write()
51 kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL); in zynqmp_fpga_ops_write()
53 return -ENOMEM; in zynqmp_fpga_ops_write()
[all …]
/Linux-v6.1/drivers/pinctrl/
Dpinctrl-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP pin controller
11 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <linux/firmware/xlnx-zynqmp.h>
20 #include <linux/pinctrl/pinconf-generic.h>
23 #include "pinctrl-utils.h"
44 * struct zynqmp_pmux_function - a pinmux function
48 * @node: Firmware node matching with the function
60 * struct zynqmp_pinctrl - driver data
80 * struct zynqmp_pctrl_group - Pin control group info
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/mailbox/
Dxlnx,zynqmp-ipi-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/mailbox/xlnx,zynqmp-ipi-mailbox.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
14 +-------------------------------------+
15 | Xilinx ZynqMP IPI Controller |
16 +-------------------------------------+
17 +--------------------------------------------------+
18 TF-A | |
21 +--------------------------+ |
[all …]
/Linux-v6.1/drivers/crypto/xilinx/
Dzynqmp-sha.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx ZynqMP SHA Driver.
12 #include <linux/dma-mapping.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
56 tfm_ctx->dev = drv_ctx->dev; in zynqmp_sha_init_tfm()
64 tfm_ctx->fbk_tfm = fallback_tfm; in zynqmp_sha_init_tfm()
65 hash->descsize += crypto_shash_descsize(tfm_ctx->fbk_tfm); in zynqmp_sha_init_tfm()
74 if (tfm_ctx->fbk_tfm) { in zynqmp_sha_exit_tfm()
75 crypto_free_shash(tfm_ctx->fbk_tfm); in zynqmp_sha_exit_tfm()
76 tfm_ctx->fbk_tfm = NULL; in zynqmp_sha_exit_tfm()
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/pinctrl/
Dxlnx,zynqmp-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP Pinctrl
10 - Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
11 - Rajan Vaja <rajan.vaja@xilinx.com>
14 Please refer to pinctrl-bindings.txt in this directory for details of the
18 ZynqMP's pin configuration nodes act as a container for an arbitrary number of
22 parameters, such as pull-up, slew rate, etc.
[all …]
/Linux-v6.1/drivers/soc/xilinx/
Dzynqmp_pm_domains.c1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP Generic PM domain support
5 * Copyright (C) 2015-2019 Xilinx, Inc.
20 #include <linux/firmware/xlnx-zynqmp.h>
27 * struct zynqmp_pm_domain - Wrapper around struct generic_pm_domain
42 * zynqmp_gpd_is_active_wakeup_path() - Check if device is in wakeup source
65 * zynqmp_gpd_power_on() - Power on PM domain
78 ret = zynqmp_pm_set_requirement(pd->node_id, in zynqmp_gpd_power_on()
83 dev_err(&domain->dev, in zynqmp_gpd_power_on()
85 ZYNQMP_PM_CAPABILITY_ACCESS, pd->node_id, ret); in zynqmp_gpd_power_on()
[all …]
Dzynqmp_power.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2019 Xilinx, Inc.
18 #include <linux/firmware/xlnx-zynqmp.h>
19 #include <linux/firmware/xlnx-event-manager.h>
20 #include <linux/mailbox/zynqmp-ipi-message.h>
23 * struct zynqmp_pm_work_struct - Wrapper for struct work_struct
46 [PM_SUSPEND_MODE_POWER_OFF] = "power-off",
59 if (work_pending(&zynqmp_pm_init_suspend_work->callback_work)) in suspend_event_callback()
63 memcpy(zynqmp_pm_init_suspend_work->args, &payload[1], in suspend_event_callback()
64 sizeof(zynqmp_pm_init_suspend_work->args)); in suspend_event_callback()
[all …]
/Linux-v6.1/drivers/gpio/
Dgpio-zynqmp-modepin.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the ps-mode pin configuration.
16 #include <linux/firmware/xlnx-zynqmp.h>
18 /* 4-bit boot mode pins */
22 * modepin_gpio_get_value - Get the state of the specified pin of GPIO device
28 * Return: 0 if the pin is low, 1 if pin is high, -EINVAL wrong pin configured
50 * modepin_gpio_set_value - Modify the state of the pin with specified value
83 * modepin_gpio_dir_in - Set the direction of the specified GPIO pin as input
95 * modepin_gpio_dir_out - Set the direction of the specified GPIO pin as output
109 * modepin_gpio_probe - Initialization method for modepin_gpio
[all …]

12