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/Linux-v5.10/drivers/media/platform/mtk-vpu/
Dmtk_vpu.c23 * VPU (video processor unit) is a tiny processor controlling video hardware
25 * VPU interfaces with other blocks by share memory and interrupt.
43 /* the size of share buffer between Host and VPU */
63 /* vpu inter-processor communication interrupt */
67 * enum vpu_fw_type - VPU firmware type
79 * struct vpu_mem - VPU extended program/data memory information
81 * @va: the kernel virtual memory address of VPU extended memory
82 * @pa: the physical memory address of VPU extended memory
91 * struct vpu_regs - VPU TCM and configuration registers
93 * @tcm: the register for VPU Tightly-Coupled Memory
[all …]
Dmtk_vpu.h13 * VPU (video processor unit) is a tiny processor controlling video hardware
15 * VPU interfaces with other blocks by share memory and interrupt.
25 * @IPI_VPU_INIT: The interrupt from vpu is to notfiy kernel
26 * VPU initialization completed.
27 * IPI_VPU_INIT is sent from VPU when firmware is
29 * command to VPU.
31 * to VPU to trigger the interrupt.
32 * @IPI_VDEC_H264: The interrupt from vpu is to notify kernel to
40 * @IPI_VDEC_VP9: The interrupt from vpu is to notify kernel to
44 * @IPI_VENC_H264: The interrupt from vpu is to notify kernel to
[all …]
/Linux-v5.10/drivers/media/platform/mtk-vcodec/
Dvdec_vpu_if.c15 struct vdec_vpu_inst *vpu = (struct vdec_vpu_inst *) in handle_init_ack_msg() local
18 mtk_vcodec_debug(vpu, "+ ap_inst_addr = 0x%llx", msg->ap_inst_addr); in handle_init_ack_msg()
20 /* mapping VPU address to kernel virtual address */ in handle_init_ack_msg()
21 /* the content in vsi is initialized to 0 in VPU */ in handle_init_ack_msg()
22 vpu->vsi = mtk_vcodec_fw_map_dm_addr(vpu->ctx->dev->fw_handler, in handle_init_ack_msg()
24 vpu->inst_addr = msg->vpu_inst_addr; in handle_init_ack_msg()
26 mtk_vcodec_debug(vpu, "- vpu_inst_addr = 0x%x", vpu->inst_addr); in handle_init_ack_msg()
30 * vpu_dec_ipi_handler - Handler for VPU ipi message.
37 * from VPU.
42 struct vdec_vpu_inst *vpu = (struct vdec_vpu_inst *) in vpu_dec_ipi_handler() local
[all …]
Dvenc_vpu_if.c12 static void handle_enc_init_msg(struct venc_vpu_inst *vpu, const void *data) in handle_enc_init_msg() argument
16 vpu->inst_addr = msg->vpu_inst_addr; in handle_enc_init_msg()
17 vpu->vsi = mtk_vcodec_fw_map_dm_addr(vpu->ctx->dev->fw_handler, in handle_enc_init_msg()
21 if (vpu->ctx->dev->venc_pdata->chip == MTK_MT8173) in handle_enc_init_msg()
25 mtk_vcodec_debug(vpu, "firmware version: 0x%x\n", in handle_enc_init_msg()
31 mtk_vcodec_err(vpu, "unhandled firmware version 0x%x\n", in handle_enc_init_msg()
33 vpu->failure = 1; in handle_enc_init_msg()
38 static void handle_enc_encode_msg(struct venc_vpu_inst *vpu, const void *data) in handle_enc_encode_msg() argument
42 vpu->state = msg->state; in handle_enc_encode_msg()
43 vpu->bs_size = msg->bs_size; in handle_enc_encode_msg()
[all …]
Dvdec_vpu_if.h15 * struct vdec_vpu_inst - VPU instance for video codec
17 * @vsi : driver structure allocated by VPU side and shared to AP side
19 * @failure : VPU execution result status, 0: success, others: fail
20 * @inst_addr : VPU decoder instance address
21 * @signaled : 1 - Host has received ack message from VPU, 0 - not received
23 * @dev : platform device of VPU
24 * @wq : wait queue to wait VPU message ack
39 * vpu_dec_init - init decoder instance and allocate required resource in VPU.
41 * @vpu: instance for vdec_vpu_inst
43 int vpu_dec_init(struct vdec_vpu_inst *vpu);
[all …]
Dvenc_ipi_msg.h16 * enum venc_ipi_msg_id - message id between AP and VPU
18 * @AP_IPIMSG_ENC_XXX: AP to VPU cmd message id
19 * @VPU_IPIMSG_ENC_XXX_DONE: VPU ack AP cmd message id
34 * struct venc_ap_ipi_msg_init - AP to VPU init cmd structure
36 * @reserved: reserved for future use. vpu is running in 32bit. Without
38 * will be different between kernel and vpu
49 * struct venc_ap_ipi_msg_set_param - AP to VPU set_param cmd structure
51 * @vpu_inst_addr: VPU encoder instance addr
71 * struct venc_ap_ipi_msg_enc - AP to VPU enc cmd structure
73 * @vpu_inst_addr: VPU encoder instance addr
[all …]
Dvenc_vpu_if.h14 * struct venc_vpu_inst - encoder VPU driver instance
15 * @wq_hd: wait queue used for vpu cmd trigger then wait vpu interrupt done
16 * @signaled: flag used for checking vpu interrupt done
17 * @failure: flag to show vpu cmd succeeds or not
21 * @inst_addr: VPU instance addr
22 * @vsi: driver structure allocated by VPU side and shared to AP side for
41 int vpu_enc_init(struct venc_vpu_inst *vpu);
42 int vpu_enc_set_param(struct venc_vpu_inst *vpu,
45 int vpu_enc_encode(struct venc_vpu_inst *vpu, unsigned int bs_mode,
50 int vpu_enc_deinit(struct venc_vpu_inst *vpu);
Dvdec_ipi_msg.h11 * enum vdec_ipi_msgid - message id between AP and VPU
12 * @AP_IPIMSG_XXX : AP to VPU cmd message id
13 * @VPU_IPIMSG_XXX_ACK : VPU ack AP cmd message id
30 * struct vdec_ap_ipi_cmd - generic AP to VPU ipi command format
32 * @vpu_inst_addr : VPU decoder instance address
40 * struct vdec_vpu_ipi_ack - generic VPU to AP ipi command format
42 * @status : VPU exeuction result
66 * @vpu_inst_addr : VPU decoder instance address
83 * @status : VPU exeuction result
85 * @vpu_inst_addr : VPU decoder instance address
/Linux-v5.10/drivers/remoteproc/
Dingenic_rproc.c48 * struct vpu - Ingenic VPU remoteproc private structure
50 * @clks: pointers to the VPU and AUX clocks
56 struct vpu { struct
66 struct vpu *vpu = rproc->priv; in ingenic_rproc_prepare() local
70 ret = clk_bulk_prepare_enable(ARRAY_SIZE(vpu->clks), vpu->clks); in ingenic_rproc_prepare()
72 dev_err(vpu->dev, "Unable to start clocks: %d\n", ret); in ingenic_rproc_prepare()
79 struct vpu *vpu = rproc->priv; in ingenic_rproc_unprepare() local
81 clk_bulk_disable_unprepare(ARRAY_SIZE(vpu->clks), vpu->clks); in ingenic_rproc_unprepare()
88 struct vpu *vpu = rproc->priv; in ingenic_rproc_start() local
91 enable_irq(vpu->irq); in ingenic_rproc_start()
[all …]
/Linux-v5.10/drivers/staging/media/hantro/
Dhantro_drv.c3 * Hantro VPU codec driver
31 #define DRIVER_NAME "hantro-vpu"
59 static void hantro_job_finish(struct hantro_dev *vpu, in hantro_job_finish() argument
65 pm_runtime_mark_last_busy(vpu->dev); in hantro_job_finish()
66 pm_runtime_put_autosuspend(vpu->dev); in hantro_job_finish()
67 clk_bulk_disable(vpu->variant->num_clocks, vpu->clocks); in hantro_job_finish()
84 void hantro_irq_done(struct hantro_dev *vpu, in hantro_irq_done() argument
88 v4l2_m2m_get_curr_priv(vpu->m2m_dev); in hantro_irq_done()
95 if (cancel_delayed_work(&vpu->watchdog_work)) { in hantro_irq_done()
98 hantro_job_finish(vpu, ctx, result); in hantro_irq_done()
[all …]
Dimx8m_vpu_hw.c3 * Hantro VPU codec driver
27 static void imx8m_soft_reset(struct hantro_dev *vpu, u32 reset_bits) in imx8m_soft_reset() argument
32 val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
34 writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
39 val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
41 writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
44 static void imx8m_clk_enable(struct hantro_dev *vpu, u32 clock_bits) in imx8m_clk_enable() argument
48 val = readl(vpu->ctrl_base + CTRL_CLOCK_ENABLE); in imx8m_clk_enable()
50 writel(val, vpu->ctrl_base + CTRL_CLOCK_ENABLE); in imx8m_clk_enable()
53 static int imx8mq_runtime_resume(struct hantro_dev *vpu) in imx8mq_runtime_resume() argument
[all …]
Dhantro_postproc.c15 #define HANTRO_PP_REG_WRITE(vpu, reg_name, val) \ argument
17 hantro_reg_write(vpu, \
18 &(vpu)->variant->postproc_regs->reg_name, \
22 #define HANTRO_PP_REG_WRITE_S(vpu, reg_name, val) \ argument
24 hantro_reg_write_s(vpu, \
25 &(vpu)->variant->postproc_regs->reg_name, \
55 struct hantro_dev *vpu = ctx->dev; in hantro_postproc_enable() local
60 if (!vpu->variant->postproc_regs) in hantro_postproc_enable()
64 HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x1); in hantro_postproc_enable()
82 HANTRO_PP_REG_WRITE(vpu, clk_gate, 0x1); in hantro_postproc_enable()
[all …]
Drk3399_vpu_hw_jpeg_enc.c3 * Hantro VPU codec driver
9 * The VPU JPEG encoder produces JPEG baseline sequential format.
35 static void rk3399_vpu_set_src_img_ctrl(struct hantro_dev *vpu, in rk3399_vpu_set_src_img_ctrl() argument
46 vepu_write_relaxed(vpu, reg, VEPU_REG_INPUT_LUMA_INFO); in rk3399_vpu_set_src_img_ctrl()
56 vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_OVER_FILL_STRM_OFFSET); in rk3399_vpu_set_src_img_ctrl()
59 vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_CTRL1); in rk3399_vpu_set_src_img_ctrl()
62 static void rk3399_vpu_jpeg_enc_set_buffers(struct hantro_dev *vpu, in rk3399_vpu_jpeg_enc_set_buffers() argument
71 vepu_write_relaxed(vpu, ctx->jpeg_enc.bounce_buffer.dma, in rk3399_vpu_jpeg_enc_set_buffers()
73 vepu_write_relaxed(vpu, ctx->jpeg_enc.bounce_buffer.size, in rk3399_vpu_jpeg_enc_set_buffers()
78 vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0); in rk3399_vpu_jpeg_enc_set_buffers()
[all …]
Dhantro_h1_jpeg_enc.c3 * Hantro VPU codec driver
18 static void hantro_h1_set_src_img_ctrl(struct hantro_dev *vpu, in hantro_h1_set_src_img_ctrl() argument
28 vepu_write_relaxed(vpu, reg, H1_REG_IN_IMG_CTRL); in hantro_h1_set_src_img_ctrl()
31 static void hantro_h1_jpeg_enc_set_buffers(struct hantro_dev *vpu, in hantro_h1_jpeg_enc_set_buffers() argument
40 vepu_write_relaxed(vpu, ctx->jpeg_enc.bounce_buffer.dma, in hantro_h1_jpeg_enc_set_buffers()
42 vepu_write_relaxed(vpu, ctx->jpeg_enc.bounce_buffer.size, in hantro_h1_jpeg_enc_set_buffers()
48 vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0); in hantro_h1_jpeg_enc_set_buffers()
52 vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0); in hantro_h1_jpeg_enc_set_buffers()
53 vepu_write_relaxed(vpu, src[1], H1_REG_ADDR_IN_PLANE_1); in hantro_h1_jpeg_enc_set_buffers()
58 vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0); in hantro_h1_jpeg_enc_set_buffers()
[all …]
Drk3399_vpu_hw.c3 * Hantro VPU codec driver
93 struct hantro_dev *vpu = dev_id; in rk3399_vepu_irq() local
97 status = vepu_read(vpu, VEPU_REG_INTERRUPT); in rk3399_vepu_irq()
101 vepu_write(vpu, 0, VEPU_REG_INTERRUPT); in rk3399_vepu_irq()
102 vepu_write(vpu, 0, VEPU_REG_AXI_CTRL); in rk3399_vepu_irq()
104 hantro_irq_done(vpu, state); in rk3399_vepu_irq()
111 struct hantro_dev *vpu = dev_id; in rk3399_vdpu_irq() local
115 status = vdpu_read(vpu, VDPU_REG_INTERRUPT); in rk3399_vdpu_irq()
119 vdpu_write(vpu, 0, VDPU_REG_INTERRUPT); in rk3399_vdpu_irq()
120 vdpu_write(vpu, 0, VDPU_REG_AXI_CTRL); in rk3399_vdpu_irq()
[all …]
Drk3288_vpu_hw.c3 * Hantro VPU codec driver
114 struct hantro_dev *vpu = dev_id; in rk3288_vepu_irq() local
118 status = vepu_read(vpu, H1_REG_INTERRUPT); in rk3288_vepu_irq()
122 vepu_write(vpu, 0, H1_REG_INTERRUPT); in rk3288_vepu_irq()
123 vepu_write(vpu, 0, H1_REG_AXI_CTRL); in rk3288_vepu_irq()
125 hantro_irq_done(vpu, state); in rk3288_vepu_irq()
132 struct hantro_dev *vpu = dev_id; in rk3288_vdpu_irq() local
136 status = vdpu_read(vpu, G1_REG_INTERRUPT); in rk3288_vdpu_irq()
140 vdpu_write(vpu, 0, G1_REG_INTERRUPT); in rk3288_vdpu_irq()
141 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in rk3288_vdpu_irq()
[all …]
Drk3399_vpu_hw_vp8_dec.c3 * Rockchip VPU codec vp8 decode driver
281 struct hantro_dev *vpu = ctx->dev; in cfg_lf() local
286 hantro_reg_write(vpu, &vp8_dec_lf_level[0], lf->level); in cfg_lf()
292 hantro_reg_write(vpu, &vp8_dec_lf_level[i], lf_level); in cfg_lf()
296 hantro_reg_write(vpu, &vp8_dec_lf_level[i], in cfg_lf()
303 vdpu_write_relaxed(vpu, reg, VDPU_REG_FILTER_MB_ADJ); in cfg_lf()
307 hantro_reg_write(vpu, &vp8_dec_mb_adj[i], in cfg_lf()
309 hantro_reg_write(vpu, &vp8_dec_ref_adj[i], in cfg_lf()
320 struct hantro_dev *vpu = ctx->dev; in cfg_qp() local
324 hantro_reg_write(vpu, &vp8_dec_quant[0], q->y_ac_qi); in cfg_qp()
[all …]
Dhantro_g1_h264_dec.c3 * Rockchip RK3288 VPU codec driver
29 struct hantro_dev *vpu = ctx->dev; in set_params() local
50 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL0); in set_params()
56 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL1); in set_params()
66 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL2); in set_params()
72 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL3); in set_params()
86 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL4); in set_params()
101 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL5); in set_params()
108 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL6); in set_params()
111 vdpu_write_relaxed(vpu, 0, G1_REG_ERR_CONC); in set_params()
[all …]
Drk3399_vpu_hw_mpeg2_dec.c3 * Hantro VPU codec driver
87 rk3399_vpu_mpeg2_dec_set_quantization(struct hantro_dev *vpu, in rk3399_vpu_mpeg2_dec_set_quantization() argument
95 vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma, in rk3399_vpu_mpeg2_dec_set_quantization()
100 rk3399_vpu_mpeg2_dec_set_buffers(struct hantro_dev *vpu, in rk3399_vpu_mpeg2_dec_set_buffers() argument
123 vdpu_write_relaxed(vpu, addr, VDPU_REG_RLC_VLC_BASE); in rk3399_vpu_mpeg2_dec_set_buffers()
131 vdpu_write_relaxed(vpu, addr, VDPU_REG_DEC_OUT_BASE); in rk3399_vpu_mpeg2_dec_set_buffers()
145 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE); in rk3399_vpu_mpeg2_dec_set_buffers()
146 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER1_BASE); in rk3399_vpu_mpeg2_dec_set_buffers()
148 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE); in rk3399_vpu_mpeg2_dec_set_buffers()
149 vdpu_write_relaxed(vpu, current_addr, VDPU_REG_REFER1_BASE); in rk3399_vpu_mpeg2_dec_set_buffers()
[all …]
Dhantro_g1_vp8_dec.c140 struct hantro_dev *vpu = ctx->dev; in cfg_lf() local
145 hantro_reg_write(vpu, &vp8_dec_lf_level[0], lf->level); in cfg_lf()
151 hantro_reg_write(vpu, &vp8_dec_lf_level[i], lf_level); in cfg_lf()
155 hantro_reg_write(vpu, &vp8_dec_lf_level[i], in cfg_lf()
162 vdpu_write_relaxed(vpu, reg, G1_REG_REF_PIC(0)); in cfg_lf()
166 hantro_reg_write(vpu, &vp8_dec_mb_adj[i], in cfg_lf()
168 hantro_reg_write(vpu, &vp8_dec_ref_adj[i], in cfg_lf()
182 struct hantro_dev *vpu = ctx->dev; in cfg_qp() local
186 hantro_reg_write(vpu, &vp8_dec_quant[0], q->y_ac_qi); in cfg_qp()
192 hantro_reg_write(vpu, &vp8_dec_quant[i], quant); in cfg_qp()
[all …]
Dhantro.h3 * Hantro VPU codec driver
51 * struct hantro_variant - information about VPU hardware variant
53 * @enc_offset: Offset from VPU base to encoder registers.
54 * @dec_offset: Offset from VPU base to decoder registers.
84 int (*init)(struct hantro_dev *vpu);
85 int (*runtime_resume)(struct hantro_dev *vpu);
122 * struct hantro_func - Hantro VPU functionality
163 * @pdev: Pointer to VPU platform device.
167 * @reg_bases: Mapped addresses of VPU registers.
168 * @enc_base: Mapped address of VPU encoder register for convenience.
[all …]
Dhantro_g1_mpeg2_dec.c3 * Hantro VPU codec driver
85 hantro_g1_mpeg2_dec_set_quantization(struct hantro_dev *vpu, in hantro_g1_mpeg2_dec_set_quantization() argument
94 vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma, in hantro_g1_mpeg2_dec_set_quantization()
99 hantro_g1_mpeg2_dec_set_buffers(struct hantro_dev *vpu, struct hantro_ctx *ctx, in hantro_g1_mpeg2_dec_set_buffers() argument
121 vdpu_write_relaxed(vpu, addr, G1_REG_RLC_VLC_BASE); in hantro_g1_mpeg2_dec_set_buffers()
129 vdpu_write_relaxed(vpu, addr, G1_REG_DEC_OUT_BASE); in hantro_g1_mpeg2_dec_set_buffers()
143 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER0_BASE); in hantro_g1_mpeg2_dec_set_buffers()
144 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER1_BASE); in hantro_g1_mpeg2_dec_set_buffers()
146 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER0_BASE); in hantro_g1_mpeg2_dec_set_buffers()
147 vdpu_write_relaxed(vpu, current_addr, G1_REG_REFER1_BASE); in hantro_g1_mpeg2_dec_set_buffers()
[all …]
/Linux-v5.10/drivers/media/platform/mtk-mdp/
Dmtk_mdp_vpu.c13 static inline struct mtk_mdp_ctx *vpu_to_ctx(struct mtk_mdp_vpu *vpu) in vpu_to_ctx() argument
15 return container_of(vpu, struct mtk_mdp_ctx, vpu); in vpu_to_ctx()
20 struct mtk_mdp_vpu *vpu = (struct mtk_mdp_vpu *) in mtk_mdp_vpu_handle_init_ack() local
23 /* mapping VPU address to kernel virtual address */ in mtk_mdp_vpu_handle_init_ack()
24 vpu->vsi = (struct mdp_process_vsi *) in mtk_mdp_vpu_handle_init_ack()
25 vpu_mapping_dm_addr(vpu->pdev, msg->vpu_inst_addr); in mtk_mdp_vpu_handle_init_ack()
26 vpu->inst_addr = msg->vpu_inst_addr; in mtk_mdp_vpu_handle_init_ack()
34 struct mtk_mdp_vpu *vpu = (struct mtk_mdp_vpu *) in mtk_mdp_vpu_ipi_handler() local
38 vpu->failure = msg->status; in mtk_mdp_vpu_ipi_handler()
39 if (!vpu->failure) { in mtk_mdp_vpu_ipi_handler()
[all …]
/Linux-v5.10/drivers/media/platform/mtk-vcodec/vdec/
Dvdec_vp9_if.c29 * struct vp9_dram_buf - contains buffer info for vpu
45 * @reserved : reserved field used by vpu
67 * @reserved : reserved field used by vpu
88 * struct vdec_vp9_vsi - shared buffer between host and VPU firmware
90 * VPU-W/R: VPU is write/reader on this item
91 * @sf_bs_buf : super frame backup buffer (AP-W, VPU-R)
93 * (AP-R/W, VPU-R/W)
94 * @sf_next_ref_fb_idx : next available super frame (AP-W, VPU-R)
95 * @sf_frm_cnt : super frame count, filled by vpu (AP-R, VPU-W)
96 * @sf_frm_offset : super frame offset, filled by vpu (AP-R, VPU-W)
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/media/
Dcoda.txt5 called VPU (Video Processing Unit).
9 (a) "fsl,imx27-vpu" for CodaDx6 present in i.MX27
10 (b) "fsl,imx51-vpu" for CodaHx4 present in i.MX51
11 (c) "fsl,imx53-vpu" for CODA7541 present in i.MX53
12 (d) "fsl,imx6q-vpu" for CODA960 present in i.MX6q
15 - interrupts : Should contain the VPU interrupt. For CODA960,
24 vpu: vpu@63ff4000 {
25 compatible = "fsl,imx53-vpu";

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