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/Linux-v5.15/Documentation/devicetree/bindings/firmware/xilinx/
Dxlnx,zynqmp-firmware.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx firmware driver
10 - Nava kishore Manne <nava.manne@xilinx.com>
12 description: The zynqmp-firmware node describes the interface to platform
13 firmware. ZynqMP has an interface to communicate with secure firmware.
14 Firmware driver provides an interface to firmware APIs. Interface APIs
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
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/Linux-v5.15/Documentation/devicetree/bindings/clock/
Dxlnx,versal-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal clock controller
10 - Michal Simek <michal.simek@xilinx.com>
11 - Jolly Shah <jolly.shah@xilinx.com>
12 - Rajan Vaja <rajan.vaja@xilinx.com>
15 The clock controller is a hardware block of Xilinx versal clock tree. It
23 const: xlnx,versal-clk
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/Linux-v5.15/Documentation/devicetree/bindings/reset/
Dxlnx,zynqmp-reset.txt1 --------------------------------------------------------------------------
2 = Zynq UltraScale+ MPSoC and Versal reset driver binding =
3 --------------------------------------------------------------------------
4 The Zynq UltraScale+ MPSoC and Versal has several different resets.
13 - compatible: "xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform
14 "xlnx,versal-reset" for Versal platform
15 - #reset-cells: Specifies the number of cells needed to encode reset
18 -------
20 -------
22 firmware {
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/Linux-v5.15/Documentation/devicetree/bindings/fpga/
Dxlnx,versal-fpga.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,versal-fpga.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal FPGA driver.
10 - Nava kishore Manne <nava.manne@xilinx.com>
13 Device Tree Versal FPGA bindings for the Versal SoC, controlled
14 using firmware interface.
19 - enum:
20 - xlnx,versal-fpga
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/Linux-v5.15/drivers/fpga/
Dversal-fpga.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019-2021 Xilinx, Inc.
6 #include <linux/dma-mapping.h>
7 #include <linux/fpga/fpga-mgr.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
29 kbuf = dma_alloc_coherent(mgr->dev.parent, size, &dma_addr, GFP_KERNEL); in versal_fpga_ops_write()
31 return -ENOMEM; in versal_fpga_ops_write()
35 dma_free_coherent(mgr->dev.parent, size, kbuf, dma_addr); in versal_fpga_ops_write()
47 struct device *dev = &pdev->dev; in versal_fpga_probe()
51 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in versal_fpga_probe()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
52 FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
88 tristate "Technologic Systems TS-73xx SBC FPGA Manager"
92 present on the TS-73xx SBC boards.
128 safely handles AXI4MM and AXI4-Lite interfaces on a
161 Select this option to enable common support for Field-Programmable
210 the card. It also instantiates the SPI master (spi-altera) for
217 Select this option to enable PCIe driver for PCIe-based
218 Field-Programmable Gate Array (FPGA) solutions which implement
238 tristate "Xilinx Versal FPGA"
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/Linux-v5.15/drivers/usb/dwc3/
Ddwc3-xilinx.c1 // SPDX-License-Identifier: GPL-2.0
3 * dwc3-xilinx.c - Xilinx DWC3 controller specific glue driver
15 #include <linux/dma-mapping.h>
21 #include <linux/firmware/xlnx-zynqmp.h>
34 /* Versal USB Reset ID */
60 reg = readl(priv_data->regs + XLNX_USB_PHY_RST_EN); in dwc3_xlnx_mask_phy_rst()
67 writel(reg, priv_data->regs + XLNX_USB_PHY_RST_EN); in dwc3_xlnx_mask_phy_rst()
72 struct device *dev = priv_data->dev; in dwc3_xlnx_init_versal()
77 /* Assert and De-assert reset */ in dwc3_xlnx_init_versal()
88 dev_err_probe(dev, ret, "failed to De-assert Reset\n"); in dwc3_xlnx_init_versal()
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/Linux-v5.15/drivers/reset/
Dreset-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/reset-controller.h>
11 #include <linux/firmware/xlnx-zynqmp.h>
14 #define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START)
39 return zynqmp_pm_reset_assert(priv->data->reset_id + id, in zynqmp_reset_assert()
48 return zynqmp_pm_reset_assert(priv->data->reset_id + id, in zynqmp_reset_deassert()
59 err = zynqmp_pm_reset_get_status(priv->data->reset_id + id, &val); in zynqmp_reset_status()
71 return zynqmp_pm_reset_assert(priv->data->reset_id + id, in zynqmp_reset_reset()
78 return reset_spec->args[0]; in zynqmp_reset_of_xlate()
102 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); in zynqmp_reset_probe()
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/Linux-v5.15/drivers/firmware/xilinx/
Dzynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx Zynq MPSoC Firmware layer
5 * Copyright (C) 2014-2021 Xilinx, Inc.
13 #include <linux/arm-smccc.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
26 #include "zynqmp-debug.h"
35 * struct pm_api_feature_data - PM API Feature data
53 * zynqmp_pm_ret_code() - Convert PMU-FW error codes to Linux error codes
65 return -ENOTSUPP; in zynqmp_pm_ret_code()
67 return -EACCES; in zynqmp_pm_ret_code()
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/Linux-v5.15/drivers/clk/zynqmp/
Dclkc.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Xilinx
12 #include <linux/clk-provider.h>
18 #include "clk-zynqmp.h"
48 * struct clock_parent - Clock parent
60 * struct zynqmp_clock - Clock
140 * zynqmp_is_valid_clock() - Check whether clock is valid or not
148 return -ENODEV; in zynqmp_is_valid_clock()
154 * zynqmp_get_clock_name() - Get name of clock from Clock index
170 return ret == 0 ? -EINVAL : ret; in zynqmp_get_clock_name()
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/Linux-v5.15/drivers/mmc/host/
Dsdhci-of-arasan.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
28 #include "sdhci-pltfm.h"
55 * On some SoCs the syscon area has a feature where the upper 16-bits of
56 * each 32-bit register act as a write mask for the lower 16-bits. This allows
64 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
68 * @shift: Bit offset within @reg of this field (or -1 if not avail)
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