Lines Matching +full:versal +full:- +full:firmware
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Xilinx
12 #include <linux/clk-provider.h>
18 #include "clk-zynqmp.h"
48 * struct clock_parent - Clock parent
60 * struct zynqmp_clock - Clock
140 * zynqmp_is_valid_clock() - Check whether clock is valid or not
148 return -ENODEV; in zynqmp_is_valid_clock()
154 * zynqmp_get_clock_name() - Get name of clock from Clock index
170 return ret == 0 ? -EINVAL : ret; in zynqmp_get_clock_name()
174 * zynqmp_get_clock_type() - Get type of clock
190 return ret == 0 ? -EINVAL : ret; in zynqmp_get_clock_type()
194 * zynqmp_pm_clock_get_num_clocks() - Get number of clocks in system
197 * Call firmware API to get number of clocks.
216 * zynqmp_pm_clock_get_name() - Get the name of clock for given id
241 * zynqmp_pm_clock_get_topology() - Get the topology of clock for given id
295 * zynqmp_clk_register_fixed_factor() - Register fixed factor with the
327 flag = zynqmp_clk_map_common_ccf_flags(nodes->flag); in zynqmp_clk_register_fixed_factor()
338 * zynqmp_pm_clock_get_parents() - Get the first 3 parents of clock for given id
372 * zynqmp_pm_clock_get_attributes() - Get the attributes of clock for given id
397 * __zynqmp_clock_get_topology() - Get topology data of clock from firmware
400 * @response: Clock topology data received from firmware
412 for (i = 0; i < ARRAY_SIZE(response->topology); i++) { in __zynqmp_clock_get_topology()
413 type = FIELD_GET(CLK_TOPOLOGY_TYPE, response->topology[i]); in __zynqmp_clock_get_topology()
418 response->topology[i]); in __zynqmp_clock_get_topology()
421 response->topology[i]); in __zynqmp_clock_get_topology()
424 response->topology[i]); in __zynqmp_clock_get_topology()
432 * zynqmp_clock_get_topology() - Get topology of clock from firmware using
463 * __zynqmp_clock_get_parents() - Get parents info of clock from firmware
466 * @response: Clock parents data received from firmware
478 for (i = 0; i < ARRAY_SIZE(response->parents); i++) { in __zynqmp_clock_get_parents()
479 if (response->parents[i] == NA_PARENT) in __zynqmp_clock_get_parents()
483 parent->id = FIELD_GET(CLK_PARENTS_ID, response->parents[i]); in __zynqmp_clock_get_parents()
484 if (response->parents[i] == DUMMY_PARENT) { in __zynqmp_clock_get_parents()
485 strcpy(parent->name, "dummy_name"); in __zynqmp_clock_get_parents()
486 parent->flag = 0; in __zynqmp_clock_get_parents()
488 parent->flag = FIELD_GET(CLK_PARENTS_FLAGS, in __zynqmp_clock_get_parents()
489 response->parents[i]); in __zynqmp_clock_get_parents()
490 if (zynqmp_get_clock_name(parent->id, parent->name)) in __zynqmp_clock_get_parents()
500 * zynqmp_clock_get_parents() - Get parents info from firmware using PM_API
515 /* Get parents from firmware */ in zynqmp_clock_get_parents()
532 * zynqmp_get_parent_list() - Create list of parents name
555 ret = of_property_match_string(np, "clock-names", in zynqmp_get_parent_list()
562 clk_type_postfix[clk_nodes[parents[i].flag - 1]. in zynqmp_get_parent_list()
573 * zynqmp_register_clk_topology() - Register clock topology
597 * Clock name received from firmware is output clock name. in zynqmp_register_clk_topology()
600 if (j != (num_nodes - 1)) { in zynqmp_register_clk_topology()
629 * zynqmp_register_clocks() - Register clocks
662 zynqmp_data->hws[i] = in zynqmp_register_clocks()
669 if (IS_ERR(zynqmp_data->hws[i])) { in zynqmp_register_clocks()
671 clock[i].clk_name, PTR_ERR(zynqmp_data->hws[i])); in zynqmp_register_clocks()
679 * zynqmp_get_clock_info() - Get clock information from firmware using PM_API
737 * zynqmp_clk_setup() - Setup the clock framework and register clocks
753 return -ENOMEM; in zynqmp_clk_setup()
758 return -ENOMEM; in zynqmp_clk_setup()
764 zynqmp_data->num = clock_max_idx; in zynqmp_clk_setup()
771 struct device *dev = &pdev->dev; in zynqmp_clock_probe()
773 ret = zynqmp_clk_setup(dev->of_node); in zynqmp_clock_probe()
779 {.compatible = "xlnx,zynqmp-clk"},
780 {.compatible = "xlnx,versal-clk"},