| /Linux-v5.10/drivers/clk/mediatek/ |
| D | clk-mt2712.c | 756 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel",
1099 "uart_sel", 20),
1101 "uart_sel", 21),
1103 "uart_sel", 22),
1105 "uart_sel", 23),
1132 "uart_sel", 9),
1134 "uart_sel", 11),
1136 "uart_sel", 12),
1138 "uart_sel", 14),
1140 "uart_sel", 15),
[all …]
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| D | clk-mt6797.c | 339 MUX_GATE(CLK_TOP_MUX_UART, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
483 GATE_ICG0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22),
484 GATE_ICG0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23),
485 GATE_ICG0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24),
486 GATE_ICG0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25),
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| D | clk-mt8183.c | 570 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel",
849 "uart_sel", 22),
851 "uart_sel", 23),
853 "uart_sel", 24),
855 "uart_sel", 25),
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| D | clk-mt6779.c | 684 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "uart_sel", uart_parents,
923 "uart_sel", 22),
925 "uart_sel", 23),
927 "uart_sel", 24),
929 "uart_sel", 25),
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| D | clk-mt8135.c | 373 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31),
506 "uart_sel",
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| D | clk-mt2701.c | 505 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
872 "uart_sel",
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| D | clk-mt6765.c | 140 FACTOR(CLK_TOP_F_FUART, "f_fuart_ck", "uart_sel", 1, 1),
399 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
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| D | clk-mt8173.c | 553 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
721 "uart_sel",
|
| D | clk-mt7622.c | 535 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
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| D | clk-mt7629.c | 505 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
|
| /Linux-v5.10/drivers/clk/imx/ |
| D | clk-imx35.c | 66 /* 9 */ ipg, arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, enumerator
147 clk[uart_sel] = imx_clk_mux("uart_sel", base + MX35_CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel)); in _mx35_clocks_init()
148 clk[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + MX35_CCM_PDR4, 10, 6); in _mx35_clocks_init()
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| D | clk-imx6sll.c | 225 …hws[IMX6SLL_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE… in imx6sll_clocks_init()
245 hws[IMX6SLL_CLK_UART_PODF] = imx_clk_hw_divider("uart_podf", "uart_sel", base + 0x24, 0, 6); in imx6sll_clocks_init()
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| D | clk-imx6sl.c | 329 …hws[IMX6SL_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, uart_sel… in imx6sl_clocks_init()
368 …hws[IMX6SL_CLK_UART_ROOT] = imx_clk_hw_divider("uart_root", "uart_sel", b… in imx6sl_clocks_init()
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| D | clk-imx5.c | 181 clk[IMX5_CLK_UART_SEL] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2, in mx5_clocks_common_init()
183 clk[IMX5_CLK_UART_PRED] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3); in mx5_clocks_common_init()
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| D | clk-imx6ul.c | 259 …hws[IMX6UL_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(… in imx6ul_clocks_init()
301 hws[IMX6UL_CLK_UART_PODF] = imx_clk_hw_divider("uart_podf", "uart_sel", base + 0x24, 0, 6); in imx6ul_clocks_init()
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| D | clk-imx6sx.c | 296 …hws[IMX6SX_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, … in imx6sx_clocks_init()
337 …hws[IMX6SX_CLK_UART_PODF] = imx_clk_hw_divider("uart_podf", "uart_sel", bas… in imx6sx_clocks_init()
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| D | clk-imx6q.c | 632 …hws[IMX6QDL_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(ua… in imx6q_clocks_init()
731 …hws[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_hw_divider("uart_serial_podf", "uart_sel", base + 0x24… in imx6q_clocks_init()
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| /Linux-v5.10/Documentation/devicetree/bindings/clock/ |
| D | imx35-clock.yaml | 32 uart_sel 13
|
