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/Linux-v5.15/Documentation/devicetree/bindings/net/
Dadi,adin.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Ardelean <alexandru.ardelean@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
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Drenesas,etheravb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
15 - items:
16 - enum:
17 - renesas,etheravb-r8a7742 # RZ/G1H
18 - renesas,etheravb-r8a7743 # RZ/G1M
19 - renesas,etheravb-r8a7744 # RZ/G1N
20 - renesas,etheravb-r8a7745 # RZ/G1E
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Dti,dp83822.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Dan Murphy <dmurphy@ti.com>
14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
16 data over standard, twisted-pair cables or to connect to an external,
17 fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
24 - $ref: "ethernet-phy.yaml#"
30 ti,link-loss-low:
39 ti,fiber-mode:
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Damlogic,meson-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Neil Armstrong <narmstrong@baylibre.com>
12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
22 - amlogic,meson8m2-dwmac
23 - amlogic,meson-gxbb-dwmac
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Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-phy.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
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Dallwinner,sun8i-a83t-emac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - const: allwinner,sun8i-a83t-emac
17 - const: allwinner,sun8i-h3-emac
18 - const: allwinner,sun8i-r40-emac
19 - const: allwinner,sun8i-v3s-emac
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Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
16 local-mac-address:
19 $ref: /schemas/types.yaml#/definitions/uint8-array
21 - minItems: 6
24 mac-address:
29 local-mac-address property.
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Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
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Dfsl,fec.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Joakim Zhang <qiangqing.zhang@nxp.com>
13 - $ref: ethernet-controller.yaml#
18 - enum:
19 - fsl,imx25-fec
20 - fsl,imx27-fec
21 - fsl,imx28-fec
22 - fsl,imx6q-fec
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/Linux-v5.15/arch/arm64/boot/dts/renesas/
Dr8a779a0.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car V3U (R8A779A0) SoC
8 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a779a0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
28 #address-cells = <1>;
29 #size-cells = <0>;
32 compatible = "arm,cortex-a76";
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Dhihope-rzg2-ex.dtsi1 // SPDX-License-Identifier: GPL-2.0
19 pinctrl-0 = <&avb_pins>;
20 pinctrl-names = "default";
21 phy-handle = <&phy0>;
22 tx-internal-delay-ps = <2000>;
23 rx-internal-delay-ps = <1800>;
26 phy0: ethernet-phy@0 {
28 interrupt-parent = <&gpio2>;
30 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
35 pinctrl-0 = <&can0_pins>;
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Dr8a779a0-falcon.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Falcon CPU and BreakOut boards with R-Car V3U
8 /dts-v1/;
9 #include "r8a779a0-falcon-cpu.dtsi"
10 #include "r8a779a0-falcon-csi-dsi.dtsi"
11 #include "r8a779a0-falcon-ethernet.dtsi"
15 compatible = "renesas,falcon-breakout", "renesas,falcon-cpu", "renesas,r8a779a0";
23 pinctrl-0 = <&avb0_pins>;
24 pinctrl-names = "default";
25 phy-handle = <&phy0>;
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Dr8a77970-eagle.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Eagle board with R-Car V3M
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
9 /dts-v1/;
23 stdout-path = "serial0:115200n8";
26 d3p3: regulator-fixed {
27 compatible = "regulator-fixed";
28 regulator-name = "fixed-3.3V";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
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Dr8a77970-v3msk.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
21 stdout-path = "serial0:115200n8";
24 hdmi-out {
25 compatible = "hdmi-connector";
30 remote-endpoint = <&adv7511_out>;
35 lvds-decoder {
37 vcc-supply = <&vcc_d3_3v>;
40 #address-cells = <1>;
41 #size-cells = <0>;
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Dbeacon-renesom-som.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/clk/versaclock.h>
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
19 clock-frequency = <32768>;
20 clock-output-names = "osc_32k";
24 compatible = "regulator-fixed";
25 regulator-name = "fixed-1.8V";
26 regulator-min-microvolt = <1800000>;
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Dr8a77970.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car V3M (R8A77970) SoC
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
9 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/power/r8a77970-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
27 /* External CAN clock - to be overridden by boards that provide it */
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Dr8a77980.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car V3H (R8A77980) SoC
9 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/r8a77980-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
28 /* External CAN clock - to be overridden by boards that provide it */
30 compatible = "fixed-clock";
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/Linux-v5.15/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-meson8b.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
35 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one
36 * cycle of the 125MHz RGMII TX clock):
51 * internal sampling) or enable (= 1) the internal logic for RXEN and RXD[3:0]
57 * the automatically delay and skew automatically (internally).
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
62 * delay (= the counter value) when to start sampling RXEN and RXD[3:0].
66 * large input delay, the bit for that signal (RXEN = bit 0, RXD[3] = bit 1,
67 * ...) can be configured to be 1 to compensate for a delay of about 1ns.
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Ddwmac-sun8i.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
11 #include <linux/mdio-mux.h>
26 /* General notes on dwmac-sun8i:
31 /* struct emac_variant - Describe dwmac-sun8i hardware variant
37 * @soc_has_internal_phy: Does the MAC embed an internal PHY
42 * @rx_delay_max: Maximum raw value for RX delay chain
43 * @tx_delay_max: Maximum raw value for TX delay chain
45 * the RX and TX delay chain registers. A
59 /* struct sunxi_priv_data - hold all sunxi private data
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/Linux-v5.15/drivers/net/phy/
Dmicrel.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2010-2013 Micrel, Inc.
30 #include <linux/delay.h>
183 const struct kszphy_type *type = phydev->drv->driver_data; in kszphy_config_intr()
187 if (type && type->interrupt_level_mask) in kszphy_config_intr()
188 mask = type->interrupt_level_mask; in kszphy_config_intr()
200 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in kszphy_config_intr()
265 return -EINVAL; in kszphy_setup_led()
285 * unique (non-broadcast) address on a shared bus.
326 struct kszphy_priv *priv = phydev->priv; in kszphy_config_reset()
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Dintel-xway.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
32 #define XWAY_MDIO_INIT_WOL BIT(15) /* Wake-On-LAN */
36 #define XWAY_MDIO_INIT_ANE BIT(11) /* Auto-Neg error */
37 #define XWAY_MDIO_INIT_ANC BIT(10) /* Auto-Neg complete */
38 #define XWAY_MDIO_INIT_ADSC BIT(5) /* Link auto-downspeed detect */
47 #define ADVERTISED_MPD BIT(10) /* Multi-port device */
170 struct device *dev = &phydev->mdio.dev; in xway_gphy_rgmii_init()
178 /* Existing behavior was to use default pin strapping delay in rgmii in xway_gphy_rgmii_init()
179 * mode, but rgmii should have meant no delay. Warn existing users, in xway_gphy_rgmii_init()
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Dnxp-c45-tja11xx.c1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Radu Pirea <radu-nicolae.pirea@oss.nxp.com>
7 #include <linux/delay.h>
174 #define NXP_C45_SKB_CB(skb) ((struct nxp_c45_skb_cb *)(skb)->cb)
214 return phydev->irq <= 0; in nxp_c45_poll_txts()
223 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_LTC_LOAD_CTRL, in _nxp_c45_ptp_gettimex64()
225 ts->tv_nsec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
227 ts->tv_nsec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
229 ts->tv_sec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
231 ts->tv_sec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
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/Linux-v5.15/include/net/
Dmac80211.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * mac80211 <-> driver interface
5 * Copyright 2002-2005, Devicescape Software, Inc.
6 * Copyright 2006-2007 Jiri Benc <jbenc@suse.cz>
7 * Copyright 2007-2010 Johannes Berg <johannes@sipsolutions.net>
8 * Copyright 2013-2014 Intel Mobile Communications GmbH
9 * Copyright (C) 2015 - 2017 Intel Deutschland GmbH
10 * Copyright (C) 2018 - 2021 Intel Corporation
30 * only partial functionality in hard- or firmware. This document
31 * defines the interface between mac80211 and low-level hardware
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/Linux-v5.15/arch/arm/boot/dts/
Dsun8i-a83t-bananapi-m3.dts2 * Copyright 2017 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 /dts-v1/;
46 #include "sun8i-a83t.dtsi"
48 #include <dt-bindings/gpio/gpio.h>
51 model = "Banana Pi BPI-M3";
52 compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t";
60 stdout-path = "serial0:115200n8";
64 compatible = "hdmi-connector";
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/Linux-v5.15/drivers/net/wireless/ti/wlcore/
Devent.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2008-2009 Nokia Corporation
14 #include "ps.h"
64 /* Calculate the internal pointer to the fwlog structure */ in wlcore_event_fw_logger()
67 /* Calculate the internal pointers to the start and end of log buffer */ in wlcore_event_fw_logger()
75 wl1271_error("buffer read pointer out of bounds: %x not in (%x-%x)\n", in wlcore_event_fw_logger()
80 start_loc = buff_read_ptr - addr_ptr; in wlcore_event_fw_logger()
81 available_len = buff_end_ptr - buff_read_ptr; in wlcore_event_fw_logger()
91 len = actual_len - len; in wlcore_event_fw_logger()
118 /* TODO: check actual multi-role support */ in wlcore_event_rssi_trigger()
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